/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) STMicroelectronics 2016 * Author: Benjamin Gaignard <[email protected]> */ #ifndef _LINUX_STM32_GPTIMER_H_ #define _LINUX_STM32_GPTIMER_H_ #include <linux/clk.h> #include <linux/dmaengine.h> #include <linux/dma-mapping.h> #include <linux/regmap.h> #define TIM_CR1 … #define TIM_CR2 … #define TIM_SMCR … #define TIM_DIER … #define TIM_SR … #define TIM_EGR … #define TIM_CCMR1 … #define TIM_CCMR2 … #define TIM_CCER … #define TIM_CNT … #define TIM_PSC … #define TIM_ARR … #define TIM_CCRx(x) … #define TIM_CCR1 … #define TIM_CCR2 … #define TIM_CCR3 … #define TIM_CCR4 … #define TIM_BDTR … #define TIM_DCR … #define TIM_DMAR … #define TIM_TISEL … #define TIM_CR1_CEN … #define TIM_CR1_DIR … #define TIM_CR1_ARPE … #define TIM_CR2_MMS … #define TIM_CR2_MMS2 … #define TIM_SMCR_SMS … #define TIM_SMCR_TS … #define TIM_DIER_UIE … #define TIM_DIER_CCxIE(x) … #define TIM_DIER_CC1IE … #define TIM_DIER_CC2IE … #define TIM_DIER_CC3IE … #define TIM_DIER_CC4IE … #define TIM_DIER_UDE … #define TIM_DIER_CCxDE(x) … #define TIM_DIER_CC1DE … #define TIM_DIER_CC2DE … #define TIM_DIER_CC3DE … #define TIM_DIER_CC4DE … #define TIM_DIER_COMDE … #define TIM_DIER_TDE … #define TIM_SR_UIF … #define TIM_SR_CC_IF(x) … #define TIM_EGR_UG … #define TIM_CCMR_PE … #define TIM_CCMR_M1 … #define TIM_CCMR_CC1S … #define TIM_CCMR_IC1PSC … #define TIM_CCMR_CC2S … #define TIM_CCMR_IC2PSC … #define TIM_CCMR_CC1S_TI1 … #define TIM_CCMR_CC1S_TI2 … #define TIM_CCMR_CC2S_TI2 … #define TIM_CCMR_CC2S_TI1 … #define TIM_CCMR_CC3S … #define TIM_CCMR_CC4S … #define TIM_CCMR_CC3S_TI3 … #define TIM_CCMR_CC4S_TI4 … #define TIM_CCER_CCxE(x) … #define TIM_CCER_CCxP(x) … #define TIM_CCER_CCxNE(x) … #define TIM_CCER_CCxNP(x) … #define TIM_CCER_CC1E … #define TIM_CCER_CC1P … #define TIM_CCER_CC1NE … #define TIM_CCER_CC1NP … #define TIM_CCER_CC2E … #define TIM_CCER_CC2P … #define TIM_CCER_CC2NE … #define TIM_CCER_CC2NP … #define TIM_CCER_CC3E … #define TIM_CCER_CC3P … #define TIM_CCER_CC3NE … #define TIM_CCER_CC3NP … #define TIM_CCER_CC4E … #define TIM_CCER_CC4P … #define TIM_CCER_CC4NE … #define TIM_CCER_CC4NP … #define TIM_CCER_CCXE … #define TIM_BDTR_BKE(x) … #define TIM_BDTR_BKP(x) … #define TIM_BDTR_AOE … #define TIM_BDTR_MOE … #define TIM_BDTR_BKF(x) … #define TIM_DCR_DBA … #define TIM_DCR_DBL … #define MAX_TIM_PSC … #define MAX_TIM_ICPSC … #define TIM_CR2_MMS_SHIFT … #define TIM_CR2_MMS2_SHIFT … #define TIM_SMCR_SMS_SLAVE_MODE_DISABLED … #define TIM_SMCR_SMS_ENCODER_MODE_1 … #define TIM_SMCR_SMS_ENCODER_MODE_2 … #define TIM_SMCR_SMS_ENCODER_MODE_3 … #define TIM_SMCR_TS_SHIFT … #define TIM_BDTR_BKF_MASK … #define TIM_BDTR_BKF_SHIFT(x) … enum stm32_timers_dmas { … }; /* STM32 Timer may have either a unique global interrupt or 4 interrupt lines */ enum stm32_timers_irqs { … }; /** * struct stm32_timers_dma - STM32 timer DMA handling. * @completion: end of DMA transfer completion * @phys_base: control registers physical base address * @lock: protect DMA access * @chan: DMA channel in use * @chans: DMA channels available for this timer instance */ struct stm32_timers_dma { … }; struct stm32_timers { … }; #if IS_REACHABLE(CONFIG_MFD_STM32_TIMERS) int stm32_timers_dma_burst_read(struct device *dev, u32 *buf, enum stm32_timers_dmas id, u32 reg, unsigned int num_reg, unsigned int bursts, unsigned long tmo_ms); #else static inline int stm32_timers_dma_burst_read(struct device *dev, u32 *buf, enum stm32_timers_dmas id, u32 reg, unsigned int num_reg, unsigned int bursts, unsigned long tmo_ms) { return -ENODEV; } #endif #endif
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