/* SPDX-License-Identifier: GPL-2.0-or-later */ /* D-Link DL2000-based Gigabit Ethernet Adapter Linux driver */ /* Copyright (c) 2001, 2002 by D-Link Corporation Written by Edward Peng.<[email protected]> Created 03-May-2001, base on Linux' sundance.c. */ #ifndef __DL2K_H__ #define __DL2K_H__ #include <linux/module.h> #include <linux/kernel.h> #include <linux/string.h> #include <linux/timer.h> #include <linux/errno.h> #include <linux/ioport.h> #include <linux/slab.h> #include <linux/interrupt.h> #include <linux/pci.h> #include <linux/netdevice.h> #include <linux/etherdevice.h> #include <linux/skbuff.h> #include <linux/crc32.h> #include <linux/ethtool.h> #include <linux/mii.h> #include <linux/bitops.h> #include <asm/processor.h> /* Processor type for cache alignment. */ #include <asm/io.h> #include <linux/uaccess.h> #include <linux/delay.h> #include <linux/spinlock.h> #include <linux/time.h> #define TX_RING_SIZE … #define TX_QUEUE_LEN … #define RX_RING_SIZE … #define TX_TOTAL_SIZE … #define RX_TOTAL_SIZE … /* Offsets to the device registers. Unlike software-only systems, device drivers interact with complex hardware. It's not useful to define symbolic names for every register bit in the device. The name can only partially document the semantics and make the driver longer and more difficult to read. In general, only the important configuration values or bits changed multiple times should be defined symbolically. */ enum dl2x_offsets { … }; /* Bits in the interrupt status/mask registers. */ enum IntStatus_bits { … }; /* Bits in the ReceiveMode register. */ enum ReceiveMode_bits { … }; /* Bits in MACCtrl. */ enum MACCtrl_bits { … }; enum ASICCtrl_LoWord_bits { … }; enum ASICCtrl_HiWord_bits { … }; #define IPG_AC_LED_MODE … #define IPG_AC_LED_SPEED … #define IPG_AC_LED_MODE_BIT_1 … /* Transmit Frame Control bits */ enum TFC_bits { … }; /* Receive Frames Status bits */ enum RFS_bits { … }; #define MII_RESET_TIME_OUT … /* MII register */ enum _mii_reg { … }; /* PCS register */ enum _pcs_reg { … }; /* IEEE Extened Status Register */ enum _mii_esr { … }; /* PHY Specific Control Register */ #if 0 typedef union t_MII_PHY_SCR { u16 image; struct { u16 disable_jabber:1; // bit 0 u16 polarity_reversal:1; // bit 1 u16 SEQ_test:1; // bit 2 u16 _bit_3:1; // bit 3 u16 disable_CLK125:1; // bit 4 u16 mdi_crossover_mode:2; // bit 6:5 u16 enable_ext_dist:1; // bit 7 u16 _bit_8_9:2; // bit 9:8 u16 force_link:1; // bit 10 u16 assert_CRS:1; // bit 11 u16 rcv_fifo_depth:2; // bit 13:12 u16 xmit_fifo_depth:2; // bit 15:14 } bits; } PHY_SCR_t, *PPHY_SCR_t; #endif PMII_ADMIN_t; /* Physical Coding Sublayer Management (PCS) */ /* PCS control and status registers bitmap as the same as MII */ /* PCS Extended Status register bitmap as the same as MII */ /* PCS ANAR */ enum _pcs_anar { … }; /* PCS ANLPAR */ enum _pcs_anlpar { … }; PSROM_t; /* Ioctl custom data */ struct ioctl_data { … }; /* The Rx and Tx buffer descriptors. */ struct netdev_desc { … }; #define PRIV_ALIGN … /* Use __attribute__((aligned (L1_CACHE_BYTES))) to maintain alignment within the structure. */ struct netdev_private { … }; /* The station address location in the EEPROM. */ /* The struct pci_device_id consist of: vendor, device Vendor and device ID to match (or PCI_ANY_ID) subvendor, subdevice Subsystem vendor and device ID to match (or PCI_ANY_ID) class Device class to match. The class_mask tells which bits class_mask of the class are honored during the comparison. driver_data Data private to the driver. */ #define CHIP_IP1000A … static const struct pci_device_id rio_pci_tbl[] = …; MODULE_DEVICE_TABLE (pci, rio_pci_tbl); #define TX_TIMEOUT … #define PACKET_SIZE … #define MAX_JUMBO … #define RIO_IO_SIZE … #define DEFAULT_RXC … #define DEFAULT_RXT … #define DEFAULT_TXC … #define MAX_TXC … #endif /* __DL2K_H__ */
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