/* SPDX-License-Identifier: GPL-2.0 */ /****************************************************************************/ /* * fec.h -- Fast Ethernet Controller for Motorola ColdFire SoC * processors. * * (C) Copyright 2000-2005, Greg Ungerer ([email protected]) * (C) Copyright 2000-2001, Lineo (www.lineo.com) */ /****************************************************************************/ #ifndef FEC_H #define FEC_H /****************************************************************************/ #include <linux/clocksource.h> #include <linux/net_tstamp.h> #include <linux/pm_qos.h> #include <linux/bpf.h> #include <linux/ptp_clock_kernel.h> #include <linux/timecounter.h> #include <dt-bindings/firmware/imx/rsrc.h> #include <linux/firmware/imx/sci.h> #include <net/xdp.h> #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST) /* * Just figures, Motorola would have to change the offsets for * registers in the same peripheral device on different models * of the ColdFire! */ #define FEC_IEVENT … #define FEC_IMASK … #define FEC_R_DES_ACTIVE_0 … #define FEC_X_DES_ACTIVE_0 … #define FEC_ECNTRL … #define FEC_MII_DATA … #define FEC_MII_SPEED … #define FEC_MIB_CTRLSTAT … #define FEC_R_CNTRL … #define FEC_X_CNTRL … #define FEC_ADDR_LOW … #define FEC_ADDR_HIGH … #define FEC_OPD … #define FEC_TXIC0 … #define FEC_TXIC1 … #define FEC_TXIC2 … #define FEC_RXIC0 … #define FEC_RXIC1 … #define FEC_RXIC2 … #define FEC_HASH_TABLE_HIGH … #define FEC_HASH_TABLE_LOW … #define FEC_GRP_HASH_TABLE_HIGH … #define FEC_GRP_HASH_TABLE_LOW … #define FEC_X_WMRK … #define FEC_R_BOUND … #define FEC_R_FSTART … #define FEC_R_DES_START_1 … #define FEC_X_DES_START_1 … #define FEC_R_BUFF_SIZE_1 … #define FEC_R_DES_START_2 … #define FEC_X_DES_START_2 … #define FEC_R_BUFF_SIZE_2 … #define FEC_R_DES_START_0 … #define FEC_X_DES_START_0 … #define FEC_R_BUFF_SIZE_0 … #define FEC_R_FIFO_RSFL … #define FEC_R_FIFO_RSEM … #define FEC_R_FIFO_RAEM … #define FEC_R_FIFO_RAFL … #define FEC_FTRL … #define FEC_RACC … #define FEC_RCMR_1 … #define FEC_RCMR_2 … #define FEC_DMA_CFG_1 … #define FEC_DMA_CFG_2 … #define FEC_R_DES_ACTIVE_1 … #define FEC_X_DES_ACTIVE_1 … #define FEC_R_DES_ACTIVE_2 … #define FEC_X_DES_ACTIVE_2 … #define FEC_QOS_SCHEME … #define FEC_LPI_SLEEP … #define FEC_LPI_WAKE … #define FEC_MIIGSK_CFGR … #define FEC_MIIGSK_ENR … #define BM_MIIGSK_CFGR_MII … #define BM_MIIGSK_CFGR_RMII … #define BM_MIIGSK_CFGR_FRCONT_10M … #define RMON_T_DROP … #define RMON_T_PACKETS … #define RMON_T_BC_PKT … #define RMON_T_MC_PKT … #define RMON_T_CRC_ALIGN … #define RMON_T_UNDERSIZE … #define RMON_T_OVERSIZE … #define RMON_T_FRAG … #define RMON_T_JAB … #define RMON_T_COL … #define RMON_T_P64 … #define RMON_T_P65TO127 … #define RMON_T_P128TO255 … #define RMON_T_P256TO511 … #define RMON_T_P512TO1023 … #define RMON_T_P1024TO2047 … #define RMON_T_P_GTE2048 … #define RMON_T_OCTETS … #define IEEE_T_DROP … #define IEEE_T_FRAME_OK … #define IEEE_T_1COL … #define IEEE_T_MCOL … #define IEEE_T_DEF … #define IEEE_T_LCOL … #define IEEE_T_EXCOL … #define IEEE_T_MACERR … #define IEEE_T_CSERR … #define IEEE_T_SQE … #define IEEE_T_FDXFC … #define IEEE_T_OCTETS_OK … #define RMON_R_PACKETS … #define RMON_R_BC_PKT … #define RMON_R_MC_PKT … #define RMON_R_CRC_ALIGN … #define RMON_R_UNDERSIZE … #define RMON_R_OVERSIZE … #define RMON_R_FRAG … #define RMON_R_JAB … #define RMON_R_RESVD_O … #define RMON_R_P64 … #define RMON_R_P65TO127 … #define RMON_R_P128TO255 … #define RMON_R_P256TO511 … #define RMON_R_P512TO1023 … #define RMON_R_P1024TO2047 … #define RMON_R_P_GTE2048 … #define RMON_R_OCTETS … #define IEEE_R_DROP … #define IEEE_R_FRAME_OK … #define IEEE_R_CRC … #define IEEE_R_ALIGN … #define IEEE_R_MACERR … #define IEEE_R_FDXFC … #define IEEE_R_OCTETS_OK … #else #define FEC_ECNTRL … #define FEC_IEVENT … #define FEC_IMASK … #define FEC_IVEC … #define FEC_R_DES_ACTIVE_0 … #define FEC_R_DES_ACTIVE_1 … #define FEC_R_DES_ACTIVE_2 … #define FEC_X_DES_ACTIVE_0 … #define FEC_X_DES_ACTIVE_1 … #define FEC_X_DES_ACTIVE_2 … #define FEC_MII_DATA … #define FEC_MII_SPEED … #define FEC_R_BOUND … #define FEC_R_FSTART … #define FEC_X_WMRK … #define FEC_X_FSTART … #define FEC_R_CNTRL … #define FEC_MAX_FRM_LEN … #define FEC_X_CNTRL … #define FEC_ADDR_LOW … #define FEC_ADDR_HIGH … #define FEC_GRP_HASH_TABLE_HIGH … #define FEC_GRP_HASH_TABLE_LOW … #define FEC_R_DES_START_0 … #define FEC_R_DES_START_1 … #define FEC_R_DES_START_2 … #define FEC_X_DES_START_0 … #define FEC_X_DES_START_1 … #define FEC_X_DES_START_2 … #define FEC_R_BUFF_SIZE_0 … #define FEC_R_BUFF_SIZE_1 … #define FEC_R_BUFF_SIZE_2 … #define FEC_FIFO_RAM … /* Not existed in real chip * Just for pass build. */ #define FEC_RCMR_1 … #define FEC_RCMR_2 … #define FEC_DMA_CFG_1 … #define FEC_DMA_CFG_2 … #define FEC_TXIC0 … #define FEC_TXIC1 … #define FEC_TXIC2 … #define FEC_RXIC0 … #define FEC_RXIC1 … #define FEC_RXIC2 … #define FEC_LPI_SLEEP … #define FEC_LPI_WAKE … #endif /* CONFIG_M5272 */ /* * Define the buffer descriptor structure. * * Evidently, ARM SoCs have the FEC block generated in a * little endian mode so adjust endianness accordingly. */ #if defined(CONFIG_ARM) || defined(CONFIG_ARM64) #define fec32_to_cpu … #define fec16_to_cpu … #define cpu_to_fec32 … #define cpu_to_fec16 … #define __fec32 … #define __fec16 … struct bufdesc { __fec16 cbd_datlen; /* Data length */ __fec16 cbd_sc; /* Control and status info */ __fec32 cbd_bufaddr; /* Buffer address */ }; #else #define fec32_to_cpu … #define fec16_to_cpu … #define cpu_to_fec32 … #define cpu_to_fec16 … #define __fec32 … #define __fec16 … struct bufdesc { … }; #endif struct bufdesc_ex { … }; /* * The following definitions courtesy of commproc.h, which where * Copyright (c) 1997 Dan Malek ([email protected]). */ #define BD_SC_EMPTY … #define BD_SC_READY … #define BD_SC_WRAP … #define BD_SC_INTRPT … #define BD_SC_CM … #define BD_SC_ID … #define BD_SC_P … #define BD_SC_BR … #define BD_SC_FR … #define BD_SC_PR … #define BD_SC_OV … #define BD_SC_CD … /* Buffer descriptor control/status used by Ethernet receive. */ #define BD_ENET_RX_EMPTY … #define BD_ENET_RX_WRAP … #define BD_ENET_RX_INTR … #define BD_ENET_RX_LAST … #define BD_ENET_RX_FIRST … #define BD_ENET_RX_MISS … #define BD_ENET_RX_LG … #define BD_ENET_RX_NO … #define BD_ENET_RX_SH … #define BD_ENET_RX_CR … #define BD_ENET_RX_OV … #define BD_ENET_RX_CL … #define BD_ENET_RX_STATS … /* Enhanced buffer descriptor control/status used by Ethernet receive */ #define BD_ENET_RX_VLAN … /* Buffer descriptor control/status used by Ethernet transmit. */ #define BD_ENET_TX_READY … #define BD_ENET_TX_PAD … #define BD_ENET_TX_WRAP … #define BD_ENET_TX_INTR … #define BD_ENET_TX_LAST … #define BD_ENET_TX_TC … #define BD_ENET_TX_DEF … #define BD_ENET_TX_HB … #define BD_ENET_TX_LC … #define BD_ENET_TX_RL … #define BD_ENET_TX_RCMASK … #define BD_ENET_TX_UN … #define BD_ENET_TX_CSL … #define BD_ENET_TX_STATS … /* enhanced buffer descriptor control/status used by Ethernet transmit */ #define BD_ENET_TX_INT … #define BD_ENET_TX_TS … #define BD_ENET_TX_PINS … #define BD_ENET_TX_IINS … /* This device has up to three irqs on some platforms */ #define FEC_IRQ_NUM … /* Maximum number of queues supported * ENET with AVB IP can support up to 3 independent tx queues and rx queues. * User can point the queue number that is less than or equal to 3. */ #define FEC_ENET_MAX_TX_QS … #define FEC_ENET_MAX_RX_QS … #define FEC_R_DES_START(X) … #define FEC_X_DES_START(X) … #define FEC_R_BUFF_SIZE(X) … #define FEC_DMA_CFG(X) … #define DMA_CLASS_EN … #define FEC_RCMR(X) … #define IDLE_SLOPE_MASK … #define IDLE_SLOPE_1 … #define IDLE_SLOPE_2 … #define IDLE_SLOPE(X) … #define RCMR_MATCHEN … #define RCMR_CMP_CFG(v, n) … #define RCMR_CMP_1 … #define RCMR_CMP_2 … #define RCMR_CMP(X) … #define FEC_TX_BD_FTYPE(X) … /* The number of Tx and Rx buffers. These are allocated from the page * pool. The code may assume these are power of two, so it it best * to keep them that size. * We don't need to allocate pages for the transmitter. We just use * the skbuffer directly. */ #define FEC_ENET_XDP_HEADROOM … #define FEC_ENET_RX_PAGES … #define FEC_ENET_RX_FRSIZE … #define FEC_ENET_RX_FRPPG … #define RX_RING_SIZE … #define FEC_ENET_TX_FRSIZE … #define FEC_ENET_TX_FRPPG … #define TX_RING_SIZE … #define TX_RING_MOD_MASK … #define BD_ENET_RX_INT … #define BD_ENET_RX_PTP … #define BD_ENET_RX_ICE … #define BD_ENET_RX_PCR … #define FLAG_RX_CSUM_ENABLED … #define FLAG_RX_CSUM_ERROR … /* Interrupt events/masks. */ #define FEC_ENET_HBERR … #define FEC_ENET_BABR … #define FEC_ENET_BABT … #define FEC_ENET_GRA … #define FEC_ENET_TXF_0 … #define FEC_ENET_TXF_1 … #define FEC_ENET_TXF_2 … #define FEC_ENET_TXB … #define FEC_ENET_RXF_0 … #define FEC_ENET_RXF_1 … #define FEC_ENET_RXF_2 … #define FEC_ENET_RXB … #define FEC_ENET_MII … #define FEC_ENET_EBERR … #define FEC_ENET_WAKEUP … #define FEC_ENET_TXF … #define FEC_ENET_RXF … #define FEC_ENET_RXF_GET(X) … #define FEC_ENET_TS_AVAIL … #define FEC_ENET_TS_TIMER … #define FEC_DEFAULT_IMASK … #define FEC_RX_DISABLED_IMASK … #define FEC_ENET_TXC_DLY … #define FEC_ENET_RXC_DLY … /* ENET interrupt coalescing macro define */ #define FEC_ITR_CLK_SEL … #define FEC_ITR_EN … #define FEC_ITR_ICFT(X) … #define FEC_ITR_ICTT(X) … #define FEC_ITR_ICFT_DEFAULT … #define FEC_ITR_ICTT_DEFAULT … #define FEC_VLAN_TAG_LEN … #define FEC_ETHTYPE_LEN … /* Controller is ENET-MAC */ #define FEC_QUIRK_ENET_MAC … /* Controller needs driver to swap frame */ #define FEC_QUIRK_SWAP_FRAME … /* Controller uses gasket */ #define FEC_QUIRK_USE_GASKET … /* Controller has GBIT support */ #define FEC_QUIRK_HAS_GBIT … /* Controller has extend desc buffer */ #define FEC_QUIRK_HAS_BUFDESC_EX … /* Controller has hardware checksum support */ #define FEC_QUIRK_HAS_CSUM … /* Controller has hardware vlan support */ #define FEC_QUIRK_HAS_VLAN … /* ENET IP errata ERR006358 * * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously * detected as not set during a prior frame transmission, then the * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in * frames not being transmitted until there is a 0-to-1 transition on * ENET_TDAR[TDAR]. */ #define FEC_QUIRK_ERR006358 … /* ENET IP hw AVB * * i.MX6SX ENET IP add Audio Video Bridging (AVB) feature support. * - Two class indicators on receive with configurable priority * - Two class indicators and line speed timer on transmit allowing * implementation class credit based shapers externally * - Additional DMA registers provisioned to allow managing up to 3 * independent rings */ #define FEC_QUIRK_HAS_AVB … /* There is a TDAR race condition for mutliQ when the software sets TDAR * and the UDMA clears TDAR simultaneously or in a small window (2-4 cycles). * This will cause the udma_tx and udma_tx_arbiter state machines to hang. * The issue exist at i.MX6SX enet IP. */ #define FEC_QUIRK_ERR007885 … /* ENET Block Guide/ Chapter for the iMX6SX (PELE) address one issue: * After set ENET_ATCR[Capture], there need some time cycles before the counter * value is capture in the register clock domain. * The wait-time-cycles is at least 6 clock cycles of the slower clock between * the register clock and the 1588 clock. The 1588 ts_clk is fixed to 25Mhz, * register clock is 66Mhz, so the wait-time-cycles must be greater than 240ns * (40ns * 6). */ #define FEC_QUIRK_BUG_CAPTURE … /* Controller has only one MDIO bus */ #define FEC_QUIRK_SINGLE_MDIO … /* Controller supports RACC register */ #define FEC_QUIRK_HAS_RACC … /* Controller supports interrupt coalesc */ #define FEC_QUIRK_HAS_COALESCE … /* Interrupt doesn't wake CPU from deep idle */ #define FEC_QUIRK_ERR006687 … /* The MIB counters should be cleared and enabled during * initialisation. */ #define FEC_QUIRK_MIB_CLEAR … /* Only i.MX25/i.MX27/i.MX28 controller supports FRBR,FRSR registers, * those FIFO receive registers are resolved in other platforms. */ #define FEC_QUIRK_HAS_FRREG … /* Some FEC hardware blocks need the MMFR cleared at setup time to avoid * the generation of an MII event. This must be avoided in the older * FEC blocks where it will stop MII events being generated. */ #define FEC_QUIRK_CLEAR_SETUP_MII … /* Some link partners do not tolerate the momentary reset of the REF_CLK * frequency when the RNCTL register is cleared by hardware reset. */ #define FEC_QUIRK_NO_HARD_RESET … /* i.MX6SX ENET IP supports multiple queues (3 queues), use this quirk to * represents this ENET IP. */ #define FEC_QUIRK_HAS_MULTI_QUEUES … /* i.MX8MQ ENET IP version add new feature to support IEEE 802.3az EEE * standard. For the transmission, MAC supply two user registers to set * Sleep (TS) and Wake (TW) time. */ #define FEC_QUIRK_HAS_EEE … /* i.MX8QM ENET IP version add new feture to generate delayed TXC/RXC * as an alternative option to make sure it works well with various PHYs. * For the implementation of delayed clock, ENET takes synchronized 250MHz * clocks to generate 2ns delay. */ #define FEC_QUIRK_DELAYED_CLKS_SUPPORT … /* i.MX8MQ SoC integration mix wakeup interrupt signal into "int2" interrupt line. */ #define FEC_QUIRK_WAKEUP_FROM_INT2 … /* i.MX6Q adds pm_qos support */ #define FEC_QUIRK_HAS_PMQOS … /* Not all FEC hardware block MDIOs support accesses in C45 mode. * Older blocks in the ColdFire parts do not support it. */ #define FEC_QUIRK_HAS_MDIO_C45 … struct bufdesc_prop { … }; struct fec_enet_priv_txrx_info { … }; enum { … }; enum fec_txbuf_type { … }; struct fec_tx_buffer { … }; struct fec_enet_priv_tx_q { … }; struct fec_enet_priv_rx_q { … }; struct fec_stop_mode_gpr { … }; /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and * tx_bd_base always point to the base of the buffer descriptors. The * cur_rx and cur_tx point to the currently available buffer. * The dirty_tx tracks the current buffer that is being sent by the * controller. The cur_tx and dirty_tx are equal under both completely * empty and completely full conditions. The empty/ready indicator in * the buffer descriptor determines the actual condition. */ struct fec_enet_private { … }; void fec_ptp_init(struct platform_device *pdev, int irq_idx); void fec_ptp_restore_state(struct fec_enet_private *fep); void fec_ptp_save_state(struct fec_enet_private *fep); void fec_ptp_stop(struct platform_device *pdev); void fec_ptp_start_cyclecounter(struct net_device *ndev); int fec_ptp_set(struct net_device *ndev, struct kernel_hwtstamp_config *config, struct netlink_ext_ack *extack); void fec_ptp_get(struct net_device *ndev, struct kernel_hwtstamp_config *config); /****************************************************************************/ #endif /* FEC_H */
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