/* SPDX-License-Identifier: GPL-2.0+ */ /* Copyright (c) 2016-2017 Hisilicon Limited. */ #ifndef __HCLGEVF_CMD_H #define __HCLGEVF_CMD_H #include <linux/io.h> #include <linux/types.h> #include "hnae3.h" #include "hclge_comm_cmd.h" #define HCLGEVF_CMDQ_RX_INVLD_B … #define HCLGEVF_CMDQ_RX_OUTVLD_B … struct hclgevf_hw; struct hclgevf_dev; #define HCLGEVF_SYNC_RX_RING_HEAD_EN_B … #define HCLGEVF_TQP_REG_OFFSET … #define HCLGEVF_TQP_REG_SIZE … #define HCLGEVF_TQP_MAX_SIZE_DEV_V2 … #define HCLGEVF_TQP_EXT_REG_OFFSET … struct hclgevf_tqp_map { … }; #define HCLGEVF_VECTOR_ELEMENTS_PER_CMD … enum hclgevf_int_type { … }; struct hclgevf_ctrl_vector_chain { … }; #define HCLGEVF_MSIX_OFT_ROCEE_S … #define HCLGEVF_MSIX_OFT_ROCEE_M … #define HCLGEVF_VEC_NUM_S … #define HCLGEVF_VEC_NUM_M … struct hclgevf_query_res_cmd { … }; #define HCLGEVF_GRO_EN_B … struct hclgevf_cfg_gro_status_cmd { … }; #define HCLGEVF_LINK_STS_B … #define HCLGEVF_LINK_STATUS … struct hclgevf_link_status_cmd { … }; #define HCLGEVF_RING_ID_MASK … #define HCLGEVF_TQP_ENABLE_B … struct hclgevf_cfg_com_tqp_queue_cmd { … }; struct hclgevf_cfg_tx_queue_pointer_cmd { … }; /* this bit indicates that the driver is ready for hardware reset */ #define HCLGEVF_NIC_SW_RST_RDY_B … #define HCLGEVF_NIC_SW_RST_RDY … #define HCLGEVF_NIC_CMQ_DESC_NUM … #define HCLGEVF_NIC_CMQ_DESC_NUM_S … #define HCLGEVF_QUERY_DEV_SPECS_BD_NUM … #define hclgevf_cmd_setup_basic_desc(desc, opcode, is_read) … struct hclgevf_dev_specs_0_cmd { … }; #define HCLGEVF_DEF_MAX_INT_GL … struct hclgevf_dev_specs_1_cmd { … }; int hclgevf_cmd_send(struct hclgevf_hw *hw, struct hclge_desc *desc, int num); void hclgevf_arq_init(struct hclgevf_dev *hdev); #endif
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