/* SPDX-License-Identifier: GPL-2.0+ */ /* * cpcihp_zt5550.h * * Intel/Ziatech ZT5550 CompactPCI Host Controller driver definitions * * Copyright 2002 SOMA Networks, Inc. * Copyright 2001 Intel San Luis Obispo * Copyright 2000,2001 MontaVista Software Inc. * * Send feedback to <[email protected]> */ #ifndef _CPCIHP_ZT5550_H #define _CPCIHP_ZT5550_H /* Direct registers */ #define CSR_HCINDEX … #define CSR_HCDATA … #define CSR_INTSTAT … #define CSR_INTMASK … #define CSR_CNT0CMD … #define CSR_CNT1CMD … #define CSR_CNT0 … #define CSR_CNT1 … /* Masks for interrupt bits in CSR_INTMASK direct register */ #define CNT0_INT_MASK … #define CNT1_INT_MASK … #define ENUM_INT_MASK … #define ALL_DIRECT_INTS_MASK … /* Indexed registers (through CSR_INDEX, CSR_DATA) */ #define HC_INT_MASK_REG … #define HC_STATUS_REG … #define HC_CMD_REG … #define ARB_CONFIG_GNT_REG … #define ARB_CONFIG_CFG_REG … #define ARB_CONFIG_REG … #define ISOL_CONFIG_REG … #define FAULT_STATUS_REG … #define FAULT_CONFIG_REG … #define WD_CONFIG_REG … #define HC_DIAG_REG … #define SERIAL_COMM_REG … #define SERIAL_OUT_REG … #define SERIAL_IN_REG … /* Masks for interrupt bits in HC_INT_MASK_REG indexed register */ #define SERIAL_INT_MASK … #define FAULT_INT_MASK … #define HCF_INT_MASK … #define ALL_INDEXED_INTS_MASK … /* Digital I/O port storing ENUM# */ #define ENUM_PORT … /* Mask to get to the ENUM# bit on the bus */ #define ENUM_MASK … #endif /* _CPCIHP_ZT5550_H */
Codebase Browser
linux