/* SPDX-License-Identifier: GPL-2.0-only */ /* * Huawei HiNIC PCI Express Linux driver * Copyright(c) 2017 Huawei Technologies Co., Ltd */ #ifndef HINIC_HW_WQE_H #define HINIC_HW_WQE_H #include "hinic_common.h" #define HINIC_CMDQ_CTRL_PI_SHIFT … #define HINIC_CMDQ_CTRL_CMD_SHIFT … #define HINIC_CMDQ_CTRL_MOD_SHIFT … #define HINIC_CMDQ_CTRL_ACK_TYPE_SHIFT … #define HINIC_CMDQ_CTRL_HW_BUSY_BIT_SHIFT … #define HINIC_CMDQ_CTRL_PI_MASK … #define HINIC_CMDQ_CTRL_CMD_MASK … #define HINIC_CMDQ_CTRL_MOD_MASK … #define HINIC_CMDQ_CTRL_ACK_TYPE_MASK … #define HINIC_CMDQ_CTRL_HW_BUSY_BIT_MASK … #define HINIC_CMDQ_CTRL_SET(val, member) … #define HINIC_CMDQ_CTRL_GET(val, member) … #define HINIC_CMDQ_WQE_HEADER_BUFDESC_LEN_SHIFT … #define HINIC_CMDQ_WQE_HEADER_COMPLETE_FMT_SHIFT … #define HINIC_CMDQ_WQE_HEADER_DATA_FMT_SHIFT … #define HINIC_CMDQ_WQE_HEADER_COMPLETE_REQ_SHIFT … #define HINIC_CMDQ_WQE_HEADER_COMPLETE_SECT_LEN_SHIFT … #define HINIC_CMDQ_WQE_HEADER_CTRL_LEN_SHIFT … #define HINIC_CMDQ_WQE_HEADER_TOGGLED_WRAPPED_SHIFT … #define HINIC_CMDQ_WQE_HEADER_BUFDESC_LEN_MASK … #define HINIC_CMDQ_WQE_HEADER_COMPLETE_FMT_MASK … #define HINIC_CMDQ_WQE_HEADER_DATA_FMT_MASK … #define HINIC_CMDQ_WQE_HEADER_COMPLETE_REQ_MASK … #define HINIC_CMDQ_WQE_HEADER_COMPLETE_SECT_LEN_MASK … #define HINIC_CMDQ_WQE_HEADER_CTRL_LEN_MASK … #define HINIC_CMDQ_WQE_HEADER_TOGGLED_WRAPPED_MASK … #define HINIC_CMDQ_WQE_HEADER_SET(val, member) … #define HINIC_CMDQ_WQE_HEADER_GET(val, member) … #define HINIC_SQ_CTRL_BUFDESC_SECT_LEN_SHIFT … #define HINIC_SQ_CTRL_TASKSECT_LEN_SHIFT … #define HINIC_SQ_CTRL_DATA_FORMAT_SHIFT … #define HINIC_SQ_CTRL_LEN_SHIFT … #define HINIC_SQ_CTRL_BUFDESC_SECT_LEN_MASK … #define HINIC_SQ_CTRL_TASKSECT_LEN_MASK … #define HINIC_SQ_CTRL_DATA_FORMAT_MASK … #define HINIC_SQ_CTRL_LEN_MASK … #define HINIC_SQ_CTRL_QUEUE_INFO_PLDOFF_SHIFT … #define HINIC_SQ_CTRL_QUEUE_INFO_UFO_SHIFT … #define HINIC_SQ_CTRL_QUEUE_INFO_TSO_SHIFT … #define HINIC_SQ_CTRL_QUEUE_INFO_TCPUDP_CS_SHIFT … #define HINIC_SQ_CTRL_QUEUE_INFO_MSS_SHIFT … #define HINIC_SQ_CTRL_QUEUE_INFO_SCTP_SHIFT … #define HINIC_SQ_CTRL_QUEUE_INFO_UC_SHIFT … #define HINIC_SQ_CTRL_QUEUE_INFO_PRI_SHIFT … #define HINIC_SQ_CTRL_QUEUE_INFO_PLDOFF_MASK … #define HINIC_SQ_CTRL_QUEUE_INFO_UFO_MASK … #define HINIC_SQ_CTRL_QUEUE_INFO_TSO_MASK … #define HINIC_SQ_CTRL_QUEUE_INFO_TCPUDP_CS_MASK … #define HINIC_SQ_CTRL_QUEUE_INFO_MSS_MASK … #define HINIC_SQ_CTRL_QUEUE_INFO_SCTP_MASK … #define HINIC_SQ_CTRL_QUEUE_INFO_UC_MASK … #define HINIC_SQ_CTRL_QUEUE_INFO_PRI_MASK … #define HINIC_SQ_CTRL_SET(val, member) … #define HINIC_SQ_CTRL_GET(val, member) … #define HINIC_SQ_CTRL_CLEAR(val, member) … #define HINIC_SQ_TASK_INFO0_L2HDR_LEN_SHIFT … #define HINIC_SQ_TASK_INFO0_L4_OFFLOAD_SHIFT … #define HINIC_SQ_TASK_INFO0_INNER_L3TYPE_SHIFT … #define HINIC_SQ_TASK_INFO0_VLAN_OFFLOAD_SHIFT … #define HINIC_SQ_TASK_INFO0_PARSE_FLAG_SHIFT … /* 1 bit reserved */ #define HINIC_SQ_TASK_INFO0_TSO_FLAG_SHIFT … #define HINIC_SQ_TASK_INFO0_VLAN_TAG_SHIFT … #define HINIC_SQ_TASK_INFO0_L2HDR_LEN_MASK … #define HINIC_SQ_TASK_INFO0_L4_OFFLOAD_MASK … #define HINIC_SQ_TASK_INFO0_INNER_L3TYPE_MASK … #define HINIC_SQ_TASK_INFO0_VLAN_OFFLOAD_MASK … #define HINIC_SQ_TASK_INFO0_PARSE_FLAG_MASK … /* 1 bit reserved */ #define HINIC_SQ_TASK_INFO0_TSO_FLAG_MASK … #define HINIC_SQ_TASK_INFO0_VLAN_TAG_MASK … #define HINIC_SQ_TASK_INFO0_SET(val, member) … /* 8 bits reserved */ #define HINIC_SQ_TASK_INFO1_MEDIA_TYPE_SHIFT … #define HINIC_SQ_TASK_INFO1_INNER_L4LEN_SHIFT … #define HINIC_SQ_TASK_INFO1_INNER_L3LEN_SHIFT … /* 8 bits reserved */ #define HINIC_SQ_TASK_INFO1_MEDIA_TYPE_MASK … #define HINIC_SQ_TASK_INFO1_INNER_L4LEN_MASK … #define HINIC_SQ_TASK_INFO1_INNER_L3LEN_MASK … #define HINIC_SQ_TASK_INFO1_SET(val, member) … #define HINIC_SQ_TASK_INFO2_TUNNEL_L4LEN_SHIFT … #define HINIC_SQ_TASK_INFO2_OUTER_L3LEN_SHIFT … #define HINIC_SQ_TASK_INFO2_TUNNEL_L4TYPE_SHIFT … /* 1 bit reserved */ #define HINIC_SQ_TASK_INFO2_OUTER_L3TYPE_SHIFT … /* 8 bits reserved */ #define HINIC_SQ_TASK_INFO2_TUNNEL_L4LEN_MASK … #define HINIC_SQ_TASK_INFO2_OUTER_L3LEN_MASK … #define HINIC_SQ_TASK_INFO2_TUNNEL_L4TYPE_MASK … /* 1 bit reserved */ #define HINIC_SQ_TASK_INFO2_OUTER_L3TYPE_MASK … /* 8 bits reserved */ #define HINIC_SQ_TASK_INFO2_SET(val, member) … /* 31 bits reserved */ #define HINIC_SQ_TASK_INFO4_L2TYPE_SHIFT … /* 31 bits reserved */ #define HINIC_SQ_TASK_INFO4_L2TYPE_MASK … #define HINIC_SQ_TASK_INFO4_SET(val, member) … #define HINIC_RQ_CQE_STATUS_RXDONE_SHIFT … #define HINIC_RQ_CQE_STATUS_RXDONE_MASK … #define HINIC_RQ_CQE_STATUS_CSUM_ERR_SHIFT … #define HINIC_RQ_CQE_STATUS_CSUM_ERR_MASK … #define HINIC_RQ_CQE_STATUS_GET(val, member) … #define HINIC_RQ_CQE_STATUS_CLEAR(val, member) … #define HINIC_RQ_CQE_SGE_LEN_SHIFT … #define HINIC_RQ_CQE_SGE_LEN_MASK … #define HINIC_RQ_CQE_SGE_GET(val, member) … #define HINIC_RQ_CTRL_BUFDESC_SECT_LEN_SHIFT … #define HINIC_RQ_CTRL_COMPLETE_FORMAT_SHIFT … #define HINIC_RQ_CTRL_COMPLETE_LEN_SHIFT … #define HINIC_RQ_CTRL_LEN_SHIFT … #define HINIC_RQ_CTRL_BUFDESC_SECT_LEN_MASK … #define HINIC_RQ_CTRL_COMPLETE_FORMAT_MASK … #define HINIC_RQ_CTRL_COMPLETE_LEN_MASK … #define HINIC_RQ_CTRL_LEN_MASK … #define HINIC_RQ_CTRL_SET(val, member) … #define HINIC_SQ_WQE_SIZE(nr_sges) … #define HINIC_SCMD_DATA_LEN … #define HINIC_MAX_SQ_BUFDESCS … #define HINIC_SQ_WQE_MAX_SIZE … #define HINIC_RQ_WQE_SIZE … #define HINIC_MSS_DEFAULT … #define HINIC_MSS_MIN … #define RQ_CQE_STATUS_NUM_LRO_SHIFT … #define RQ_CQE_STATUS_NUM_LRO_MASK … #define RQ_CQE_STATUS_GET(val, member) … #define HINIC_GET_RX_NUM_LRO(status) … #define RQ_CQE_OFFOLAD_TYPE_PKT_TYPE_SHIFT … #define RQ_CQE_OFFOLAD_TYPE_PKT_TYPE_MASK … #define RQ_CQE_OFFOLAD_TYPE_VLAN_EN_SHIFT … #define RQ_CQE_OFFOLAD_TYPE_VLAN_EN_MASK … #define RQ_CQE_OFFOLAD_TYPE_GET(val, member) … #define HINIC_GET_RX_PKT_TYPE(offload_type) … #define HINIC_GET_RX_VLAN_OFFLOAD_EN(offload_type) … #define RQ_CQE_SGE_VLAN_MASK … #define RQ_CQE_SGE_VLAN_SHIFT … #define RQ_CQE_SGE_GET(val, member) … #define HINIC_GET_RX_VLAN_TAG(vlan_len) … #define HINIC_RSS_TYPE_VALID_SHIFT … #define HINIC_RSS_TYPE_TCP_IPV6_EXT_SHIFT … #define HINIC_RSS_TYPE_IPV6_EXT_SHIFT … #define HINIC_RSS_TYPE_TCP_IPV6_SHIFT … #define HINIC_RSS_TYPE_IPV6_SHIFT … #define HINIC_RSS_TYPE_TCP_IPV4_SHIFT … #define HINIC_RSS_TYPE_IPV4_SHIFT … #define HINIC_RSS_TYPE_UDP_IPV6_SHIFT … #define HINIC_RSS_TYPE_UDP_IPV4_SHIFT … #define HINIC_RSS_TYPE_SET(val, member) … #define HINIC_RSS_TYPE_GET(val, member) … enum hinic_l3_offload_type { … }; enum hinic_l4_offload_type { … }; enum hinic_l4_tunnel_type { … }; enum hinic_outer_l3type { … }; enum hinic_l2type { … }; struct hinic_cmdq_header { … }; struct hinic_status { … }; struct hinic_ctrl { … }; struct hinic_sge_resp { … }; struct hinic_cmdq_completion { … }; struct hinic_scmd_bufdesc { … }; struct hinic_lcmd_bufdesc { … }; struct hinic_cmdq_wqe_scmd { … }; struct hinic_cmdq_wqe_lcmd { … }; struct hinic_cmdq_direct_wqe { … }; struct hinic_cmdq_wqe { … }; struct hinic_sq_ctrl { … }; struct hinic_sq_task { … }; struct hinic_sq_bufdesc { … }; struct hinic_sq_wqe { … }; struct hinic_rq_cqe { … }; struct hinic_rq_ctrl { … }; struct hinic_rq_cqe_sect { … }; struct hinic_rq_bufdesc { … }; struct hinic_rq_wqe { … }; struct hinic_hw_wqe { … }; #endif
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