linux/drivers/net/ethernet/huawei/hinic/hinic_hw_dev.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Huawei HiNIC PCI Express Linux driver
 * Copyright(c) 2017 Huawei Technologies Co., Ltd
 */

#ifndef HINIC_HW_DEV_H
#define HINIC_HW_DEV_H

#include <linux/pci.h>
#include <linux/types.h>
#include <linux/bitops.h>
#include <net/devlink.h>

#include "hinic_hw_if.h"
#include "hinic_hw_eqs.h"
#include "hinic_hw_mgmt.h"
#include "hinic_hw_qp.h"
#include "hinic_hw_io.h"
#include "hinic_hw_mbox.h"

#define HINIC_MAX_QPS …

#define HINIC_MGMT_NUM_MSG_CMD …

#define HINIC_PF_SET_VF_ALREADY …
#define HINIC_MGMT_STATUS_EXIST …
#define HINIC_MGMT_CMD_UNSUPPORTED …

#define HINIC_CMD_VER_FUNC_ID …

struct hinic_cap { … };

enum hw_ioctxt_set_cmdq_depth { … };

enum hinic_port_cmd { … };

/* cmd of mgmt CPU message for HILINK module */
enum hinic_hilink_cmd { … };

enum hinic_ucode_cmd { … };

#define NIC_RSS_CMD_TEMP_ALLOC …
#define NIC_RSS_CMD_TEMP_FREE …

enum hinic_mgmt_msg_cmd { … };

enum hinic_cb_state { … };

enum hinic_res_state { … };

struct hinic_cmd_fw_ctxt { … };

struct hinic_cmd_hw_ioctxt { … };

struct hinic_cmd_io_status { … };

struct hinic_cmd_clear_io_res { … };

struct hinic_cmd_set_res_state { … };

struct hinic_ceq_ctrl_reg { … };

struct hinic_cmd_base_qpn { … };

struct hinic_cmd_hw_ci { … };

struct hinic_cmd_l2nic_reset { … };

struct hinic_msix_config { … };

struct hinic_set_random_id { … };

struct hinic_board_info { … };

struct hinic_comm_board_info { … };

struct hinic_hwdev { … };

struct hinic_nic_cb { … };

#define HINIC_COMM_SELF_CMD_MAX …

comm_mgmt_self_msg_proc;

struct comm_mgmt_self_msg_sub_info { … };

struct comm_mgmt_self_msg_info { … };

struct hinic_pfhwdev { … };

struct hinic_dev_cap { … };

hinic_fault_hw_mgmt;

struct hinic_fault_event { … };

struct hinic_cmd_fault_event { … };

enum hinic_fault_type { … };

enum hinic_fault_err_level { … };

struct hinic_mgmt_watchdog_info { … };

void hinic_hwdev_cb_register(struct hinic_hwdev *hwdev,
			     enum hinic_mgmt_msg_cmd cmd, void *handle,
			     void (*handler)(void *handle, void *buf_in,
					     u16 in_size, void *buf_out,
					     u16 *out_size));

void hinic_hwdev_cb_unregister(struct hinic_hwdev *hwdev,
			       enum hinic_mgmt_msg_cmd cmd);

int hinic_port_msg_cmd(struct hinic_hwdev *hwdev, enum hinic_port_cmd cmd,
		       void *buf_in, u16 in_size, void *buf_out,
		       u16 *out_size);

int hinic_hilink_msg_cmd(struct hinic_hwdev *hwdev, enum hinic_hilink_cmd cmd,
			 void *buf_in, u16 in_size, void *buf_out,
			 u16 *out_size);

int hinic_hwdev_ifup(struct hinic_hwdev *hwdev, u16 sq_depth, u16 rq_depth);

void hinic_hwdev_ifdown(struct hinic_hwdev *hwdev);

struct hinic_hwdev *hinic_init_hwdev(struct pci_dev *pdev, struct devlink *devlink);

void hinic_free_hwdev(struct hinic_hwdev *hwdev);

int hinic_hwdev_num_qps(struct hinic_hwdev *hwdev);

struct hinic_sq *hinic_hwdev_get_sq(struct hinic_hwdev *hwdev, int i);

struct hinic_rq *hinic_hwdev_get_rq(struct hinic_hwdev *hwdev, int i);

int hinic_hwdev_msix_cnt_set(struct hinic_hwdev *hwdev, u16 msix_index);

int hinic_hwdev_msix_set(struct hinic_hwdev *hwdev, u16 msix_index,
			 u8 pending_limit, u8 coalesc_timer,
			 u8 lli_timer_cfg, u8 lli_credit_limit,
			 u8 resend_timer);

int hinic_hwdev_hw_ci_addr_set(struct hinic_hwdev *hwdev, struct hinic_sq *sq,
			       u8 pending_limit, u8 coalesc_timer);

void hinic_hwdev_set_msix_state(struct hinic_hwdev *hwdev, u16 msix_index,
				enum hinic_msix_state flag);

int hinic_set_interrupt_cfg(struct hinic_hwdev *hwdev,
			    struct hinic_msix_config *interrupt_info);

int hinic_get_board_info(struct hinic_hwdev *hwdev,
			 struct hinic_comm_board_info *board_info);

#endif