/* SPDX-License-Identifier: GPL-2.0 */ /* Copyright(c) 1999 - 2018 Intel Corporation. */ #ifndef _E1000E_80003ES2LAN_H_ #define _E1000E_80003ES2LAN_H_ #define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL … #define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL … #define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL … #define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE … #define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS … #define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS … #define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING … #define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT … #define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT … #define E1000_KMRNCTRLSTA_OPMODE_E_IDLE … #define E1000_KMRNCTRLSTA_OPMODE_MASK … #define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO … #define E1000_TCTL_EXT_GCEX_MASK … #define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN … #define DEFAULT_TIPG_IPGT_1000_80003ES2LAN … #define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN … /* GG82563 PHY Specific Status Register (Page 0, Register 16 */ #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE … #define GG82563_PSCR_CROSSOVER_MODE_MASK … #define GG82563_PSCR_CROSSOVER_MODE_MDI … #define GG82563_PSCR_CROSSOVER_MODE_MDIX … #define GG82563_PSCR_CROSSOVER_MODE_AUTO … /* PHY Specific Control Register 2 (Page 0, Register 26) */ #define GG82563_PSCR2_REVERSE_AUTO_NEG … /* MAC Specific Control Register (Page 2, Register 21) */ /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */ #define GG82563_MSCR_TX_CLK_MASK … #define GG82563_MSCR_TX_CLK_10MBPS_2_5 … #define GG82563_MSCR_TX_CLK_100MBPS_25 … #define GG82563_MSCR_TX_CLK_1000MBPS_25 … #define GG82563_MSCR_ASSERT_CRS_ON_TX … /* DSP Distance Register (Page 5, Register 26) * 0 = <50M * 1 = 50-80M * 2 = 80-100M * 3 = 110-140M * 4 = >140M */ #define GG82563_DSPD_CABLE_LENGTH … /* Kumeran Mode Control Register (Page 193, Register 16) */ #define GG82563_KMCR_PASS_FALSE_CARRIER … /* Max number of times Kumeran read/write should be validated */ #define GG82563_MAX_KMRN_RETRY … /* Power Management Control Register (Page 193, Register 20) */ /* 1=Enable SERDES Electrical Idle */ #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE … /* In-Band Control Register (Page 194, Register 18) */ #define GG82563_ICR_DIS_PADDING … #endif
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