/* SPDX-License-Identifier: GPL-2.0 */ /* Copyright(c) 2007 - 2018 Intel Corporation. */ #ifndef _E1000_I210_H_ #define _E1000_I210_H_ s32 igb_acquire_swfw_sync_i210(struct e1000_hw *hw, u16 mask); void igb_release_swfw_sync_i210(struct e1000_hw *hw, u16 mask); s32 igb_valid_led_default_i210(struct e1000_hw *hw, u16 *data); s32 igb_read_invm_version(struct e1000_hw *hw, struct e1000_fw_version *invm_ver); s32 igb_read_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, u16 *data); s32 igb_write_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, u16 data); s32 igb_init_nvm_params_i210(struct e1000_hw *hw); bool igb_get_flash_presence_i210(struct e1000_hw *hw); s32 igb_pll_workaround_i210(struct e1000_hw *hw); s32 igb_get_cfg_done_i210(struct e1000_hw *hw); #define E1000_STM_OPCODE … #define E1000_EEPROM_FLASH_SIZE_WORD … #define INVM_DWORD_TO_RECORD_TYPE(invm_dword) … #define INVM_DWORD_TO_WORD_ADDRESS(invm_dword) … #define INVM_DWORD_TO_WORD_DATA(invm_dword) … enum E1000_INVM_STRUCTURE_TYPE { … }; #define E1000_INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS … #define E1000_INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS … #define E1000_INVM_ULT_BYTES_SIZE … #define E1000_INVM_RECORD_SIZE_IN_BYTES … #define E1000_INVM_VER_FIELD_ONE … #define E1000_INVM_VER_FIELD_TWO … #define E1000_INVM_IMGTYPE_FIELD … #define E1000_INVM_MAJOR_MASK … #define E1000_INVM_MINOR_MASK … #define E1000_INVM_MAJOR_SHIFT … #define ID_LED_DEFAULT_I210 … #define ID_LED_DEFAULT_I210_SERDES … /* NVM offset defaults for i211 device */ #define NVM_INIT_CTRL_2_DEFAULT_I211 … #define NVM_INIT_CTRL_4_DEFAULT_I211 … #define NVM_LED_1_CFG_DEFAULT_I211 … #define NVM_LED_0_2_CFG_DEFAULT_I211 … /* PLL Defines */ #define E1000_PCI_PMCSR … #define E1000_PCI_PMCSR_D3 … #define E1000_MAX_PLL_TRIES … #define E1000_PHY_PLL_UNCONF … #define E1000_PHY_PLL_FREQ_PAGE … #define E1000_PHY_PLL_FREQ_REG … #define E1000_INVM_DEFAULT_AL … #define E1000_INVM_AUTOLOAD … #define E1000_INVM_PLL_WO_VAL … #endif
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