// SPDX-License-Identifier: GPL-2.0 /* Copyright (c) 2018 Intel Corporation */ #include <linux/bitfield.h> #include <linux/delay.h> #include "igc_hw.h" /** * igc_acquire_nvm_i225 - Acquire exclusive access to EEPROM * @hw: pointer to the HW structure * * Acquire the necessary semaphores for exclusive access to the EEPROM. * Set the EEPROM access request bit and wait for EEPROM access grant bit. * Return successful if access grant bit set, else clear the request for * EEPROM access and return -IGC_ERR_NVM (-1). */ static s32 igc_acquire_nvm_i225(struct igc_hw *hw) { … } /** * igc_release_nvm_i225 - Release exclusive access to EEPROM * @hw: pointer to the HW structure * * Stop any current commands to the EEPROM and clear the EEPROM request bit, * then release the semaphores acquired. */ static void igc_release_nvm_i225(struct igc_hw *hw) { … } /** * igc_get_hw_semaphore_i225 - Acquire hardware semaphore * @hw: pointer to the HW structure * * Acquire the HW semaphore to access the PHY or NVM */ static s32 igc_get_hw_semaphore_i225(struct igc_hw *hw) { … } /** * igc_acquire_swfw_sync_i225 - Acquire SW/FW semaphore * @hw: pointer to the HW structure * @mask: specifies which semaphore to acquire * * Acquire the SW/FW semaphore to access the PHY or NVM. The mask * will also specify which port we're acquiring the lock for. */ s32 igc_acquire_swfw_sync_i225(struct igc_hw *hw, u16 mask) { … } /** * igc_release_swfw_sync_i225 - Release SW/FW semaphore * @hw: pointer to the HW structure * @mask: specifies which semaphore to acquire * * Release the SW/FW semaphore used to access the PHY or NVM. The mask * will also specify which port we're releasing the lock for. */ void igc_release_swfw_sync_i225(struct igc_hw *hw, u16 mask) { … } /** * igc_read_nvm_srrd_i225 - Reads Shadow Ram using EERD register * @hw: pointer to the HW structure * @offset: offset of word in the Shadow Ram to read * @words: number of words to read * @data: word read from the Shadow Ram * * Reads a 16 bit word from the Shadow Ram using the EERD register. * Uses necessary synchronization semaphores. */ static s32 igc_read_nvm_srrd_i225(struct igc_hw *hw, u16 offset, u16 words, u16 *data) { … } /** * igc_write_nvm_srwr - Write to Shadow Ram using EEWR * @hw: pointer to the HW structure * @offset: offset within the Shadow Ram to be written to * @words: number of words to write * @data: 16 bit word(s) to be written to the Shadow Ram * * Writes data to Shadow Ram at offset using EEWR register. * * If igc_update_nvm_checksum is not called after this function , the * Shadow Ram will most likely contain an invalid checksum. */ static s32 igc_write_nvm_srwr(struct igc_hw *hw, u16 offset, u16 words, u16 *data) { … } /** * igc_write_nvm_srwr_i225 - Write to Shadow RAM using EEWR * @hw: pointer to the HW structure * @offset: offset within the Shadow RAM to be written to * @words: number of words to write * @data: 16 bit word(s) to be written to the Shadow RAM * * Writes data to Shadow RAM at offset using EEWR register. * * If igc_update_nvm_checksum is not called after this function , the * data will not be committed to FLASH and also Shadow RAM will most likely * contain an invalid checksum. * * If error code is returned, data and Shadow RAM may be inconsistent - buffer * partially written. */ static s32 igc_write_nvm_srwr_i225(struct igc_hw *hw, u16 offset, u16 words, u16 *data) { … } /** * igc_validate_nvm_checksum_i225 - Validate EEPROM checksum * @hw: pointer to the HW structure * * Calculates the EEPROM checksum by reading/adding each word of the EEPROM * and then verifies that the sum of the EEPROM is equal to 0xBABA. */ static s32 igc_validate_nvm_checksum_i225(struct igc_hw *hw) { … } /** * igc_pool_flash_update_done_i225 - Pool FLUDONE status * @hw: pointer to the HW structure */ static s32 igc_pool_flash_update_done_i225(struct igc_hw *hw) { … } /** * igc_update_flash_i225 - Commit EEPROM to the flash * @hw: pointer to the HW structure */ static s32 igc_update_flash_i225(struct igc_hw *hw) { … } /** * igc_update_nvm_checksum_i225 - Update EEPROM checksum * @hw: pointer to the HW structure * * Updates the EEPROM checksum by reading/adding each word of the EEPROM * up to the checksum. Then calculates the EEPROM checksum and writes the * value to the EEPROM. Next commit EEPROM data onto the Flash. */ static s32 igc_update_nvm_checksum_i225(struct igc_hw *hw) { … } /** * igc_get_flash_presence_i225 - Check if flash device is detected * @hw: pointer to the HW structure */ bool igc_get_flash_presence_i225(struct igc_hw *hw) { … } /** * igc_init_nvm_params_i225 - Init NVM func ptrs. * @hw: pointer to the HW structure */ s32 igc_init_nvm_params_i225(struct igc_hw *hw) { … } /** * igc_set_eee_i225 - Enable/disable EEE support * @hw: pointer to the HW structure * @adv2p5G: boolean flag enabling 2.5G EEE advertisement * @adv1G: boolean flag enabling 1G EEE advertisement * @adv100M: boolean flag enabling 100M EEE advertisement * * Enable/disable EEE based on setting in dev_spec structure. **/ s32 igc_set_eee_i225(struct igc_hw *hw, bool adv2p5G, bool adv1G, bool adv100M) { … } /* igc_set_ltr_i225 - Set Latency Tolerance Reporting thresholds * @hw: pointer to the HW structure * @link: bool indicating link status * * Set the LTR thresholds based on the link speed (Mbps), EEE, and DMAC * settings, otherwise specify that there is no LTR requirement. */ s32 igc_set_ltr_i225(struct igc_hw *hw, bool link) { … }
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