/* SPDX-License-Identifier: GPL-2.0 */ /* Copyright(c) 1999 - 2018 Intel Corporation. */ #ifndef _IXGBE_PHY_H_ #define _IXGBE_PHY_H_ #include "ixgbe_type.h" #define IXGBE_I2C_EEPROM_DEV_ADDR … #define IXGBE_I2C_EEPROM_DEV_ADDR2 … /* EEPROM byte offsets */ #define IXGBE_SFF_IDENTIFIER … #define IXGBE_SFF_IDENTIFIER_SFP … #define IXGBE_SFF_VENDOR_OUI_BYTE0 … #define IXGBE_SFF_VENDOR_OUI_BYTE1 … #define IXGBE_SFF_VENDOR_OUI_BYTE2 … #define IXGBE_SFF_1GBE_COMP_CODES … #define IXGBE_SFF_10GBE_COMP_CODES … #define IXGBE_SFF_CABLE_TECHNOLOGY … #define IXGBE_SFF_BITRATE_NOMINAL … #define IXGBE_SFF_CABLE_SPEC_COMP … #define IXGBE_SFF_SFF_8472_SWAP … #define IXGBE_SFF_SFF_8472_COMP … #define IXGBE_SFF_SFF_8472_OSCB … #define IXGBE_SFF_SFF_8472_ESCB … #define IXGBE_SFF_IDENTIFIER_QSFP_PLUS … #define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0 … #define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1 … #define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2 … #define IXGBE_SFF_QSFP_CONNECTOR … #define IXGBE_SFF_QSFP_10GBE_COMP … #define IXGBE_SFF_QSFP_1GBE_COMP … #define IXGBE_SFF_QSFP_CABLE_LENGTH … #define IXGBE_SFF_QSFP_DEVICE_TECH … /* Bitmasks */ #define IXGBE_SFF_DA_PASSIVE_CABLE … #define IXGBE_SFF_DA_ACTIVE_CABLE … #define IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING … #define IXGBE_SFF_1GBASESX_CAPABLE … #define IXGBE_SFF_1GBASELX_CAPABLE … #define IXGBE_SFF_1GBASET_CAPABLE … #define IXGBE_SFF_BASEBX10_CAPABLE … #define IXGBE_SFF_10GBASESR_CAPABLE … #define IXGBE_SFF_10GBASELR_CAPABLE … #define IXGBE_SFF_SOFT_RS_SELECT_MASK … #define IXGBE_SFF_SOFT_RS_SELECT_10G … #define IXGBE_SFF_SOFT_RS_SELECT_1G … #define IXGBE_SFF_ADDRESSING_MODE … #define IXGBE_SFF_DDM_IMPLEMENTED … #define IXGBE_SFF_QSFP_DA_ACTIVE_CABLE … #define IXGBE_SFF_QSFP_DA_PASSIVE_CABLE … #define IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE … #define IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL … #define IXGBE_I2C_EEPROM_READ_MASK … #define IXGBE_I2C_EEPROM_STATUS_MASK … #define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION … #define IXGBE_I2C_EEPROM_STATUS_PASS … #define IXGBE_I2C_EEPROM_STATUS_FAIL … #define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS … #define IXGBE_CS4227 … #define IXGBE_CS4227_GLOBAL_ID_LSB … #define IXGBE_CS4227_GLOBAL_ID_MSB … #define IXGBE_CS4227_SCRATCH … #define IXGBE_CS4227_EFUSE_PDF_SKU … #define IXGBE_CS4223_SKU_ID … #define IXGBE_CS4227_SKU_ID … #define IXGBE_CS4227_RESET_PENDING … #define IXGBE_CS4227_RESET_COMPLETE … #define IXGBE_CS4227_RETRIES … #define IXGBE_CS4227_EFUSE_STATUS … #define IXGBE_CS4227_LINE_SPARE22_MSB … #define IXGBE_CS4227_LINE_SPARE24_LSB … #define IXGBE_CS4227_HOST_SPARE22_MSB … #define IXGBE_CS4227_HOST_SPARE24_LSB … #define IXGBE_CS4227_EEPROM_STATUS … #define IXGBE_CS4227_EEPROM_LOAD_OK … #define IXGBE_CS4227_SPEED_1G … #define IXGBE_CS4227_SPEED_10G … #define IXGBE_CS4227_EDC_MODE_CX1 … #define IXGBE_CS4227_EDC_MODE_SR … #define IXGBE_CS4227_EDC_MODE_DIAG … #define IXGBE_CS4227_RESET_HOLD … #define IXGBE_CS4227_RESET_DELAY … #define IXGBE_CS4227_CHECK_DELAY … #define IXGBE_PE … #define IXGBE_PE_OUTPUT … #define IXGBE_PE_CONFIG … #define IXGBE_PE_BIT1 … /* Flow control defines */ #define IXGBE_TAF_SYM_PAUSE … #define IXGBE_TAF_ASM_PAUSE … /* Bit-shift macros */ #define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT … #define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT … #define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT … /* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */ #define IXGBE_SFF_VENDOR_OUI_TYCO … #define IXGBE_SFF_VENDOR_OUI_FTL … #define IXGBE_SFF_VENDOR_OUI_AVAGO … #define IXGBE_SFF_VENDOR_OUI_INTEL … /* I2C SDA and SCL timing parameters for standard mode */ #define IXGBE_I2C_T_HD_STA … #define IXGBE_I2C_T_LOW … #define IXGBE_I2C_T_HIGH … #define IXGBE_I2C_T_SU_STA … #define IXGBE_I2C_T_HD_DATA … #define IXGBE_I2C_T_SU_DATA … #define IXGBE_I2C_T_RISE … #define IXGBE_I2C_T_FALL … #define IXGBE_I2C_T_SU_STO … #define IXGBE_I2C_T_BUF … #define IXGBE_SFP_DETECT_RETRIES … #define IXGBE_TN_LASI_STATUS_REG … #define IXGBE_TN_LASI_STATUS_TEMP_ALARM … /* SFP+ SFF-8472 Compliance code */ #define IXGBE_SFF_SFF_8472_UNSUP … int ixgbe_mii_bus_init(struct ixgbe_hw *hw); int ixgbe_identify_phy_generic(struct ixgbe_hw *hw); int ixgbe_reset_phy_generic(struct ixgbe_hw *hw); int ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, u16 *phy_data); int ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, u16 phy_data); int ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, u16 *phy_data); int ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, u16 phy_data); int ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw); int ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, ixgbe_link_speed speed, bool autoneg_wait_to_complete); int ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed, bool *autoneg); bool ixgbe_check_reset_blocked(struct ixgbe_hw *hw); /* PHY specific */ int ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, bool *link_up); int ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw); int ixgbe_reset_phy_nl(struct ixgbe_hw *hw); int ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on); int ixgbe_identify_module_generic(struct ixgbe_hw *hw); int ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw); int ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, u16 *list_offset, u16 *data_offset); bool ixgbe_tn_check_overtemp(struct ixgbe_hw *hw); int ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, u8 *data); int ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, u8 *data); int ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, u8 data); int ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, u8 data); int ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data); int ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, u8 *sff8472_data); int ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, u8 eeprom_data); int ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *, u8 addr, u16 reg, u16 *val, bool lock); int ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *, u8 addr, u16 reg, u16 val, bool lock); #endif /* _IXGBE_PHY_H_ */
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