/* SPDX-License-Identifier: GPL-2.0 */ /* Copyright(c) 2013 - 2021 Intel Corporation. */ #ifndef _I40E_DCB_H_ #define _I40E_DCB_H_ #include "i40e_type.h" #define I40E_DCBX_STATUS_NOT_STARTED … #define I40E_DCBX_STATUS_IN_PROGRESS … #define I40E_DCBX_STATUS_DONE … #define I40E_DCBX_STATUS_MULTIPLE_PEERS … #define I40E_DCBX_STATUS_DISABLED … #define I40E_TLV_TYPE_END … #define I40E_TLV_TYPE_ORG … #define I40E_IEEE_8021QAZ_OUI … #define I40E_IEEE_SUBTYPE_ETS_CFG … #define I40E_IEEE_SUBTYPE_ETS_REC … #define I40E_IEEE_SUBTYPE_PFC_CFG … #define I40E_IEEE_SUBTYPE_APP_PRI … #define I40E_CEE_DCBX_OUI … #define I40E_CEE_DCBX_TYPE … #define I40E_CEE_SUBTYPE_CTRL … #define I40E_CEE_SUBTYPE_PG_CFG … #define I40E_CEE_SUBTYPE_PFC_CFG … #define I40E_CEE_SUBTYPE_APP_PRI … #define I40E_CEE_MAX_FEAT_TYPE … #define I40E_LLDP_CURRENT_STATUS_XL710_OFFSET … #define I40E_LLDP_CURRENT_STATUS_X722_OFFSET … #define I40E_LLDP_CURRENT_STATUS_OFFSET … #define I40E_LLDP_CURRENT_STATUS_SIZE … /* Defines for LLDP TLV header */ #define I40E_LLDP_TLV_LEN_SHIFT … #define I40E_LLDP_TLV_LEN_MASK … #define I40E_LLDP_TLV_TYPE_SHIFT … #define I40E_LLDP_TLV_TYPE_MASK … #define I40E_LLDP_TLV_SUBTYPE_SHIFT … #define I40E_LLDP_TLV_SUBTYPE_MASK … #define I40E_LLDP_TLV_OUI_SHIFT … #define I40E_LLDP_TLV_OUI_MASK … /* Defines for IEEE ETS TLV */ #define I40E_IEEE_ETS_MAXTC_SHIFT … #define I40E_IEEE_ETS_MAXTC_MASK … #define I40E_IEEE_ETS_CBS_SHIFT … #define I40E_IEEE_ETS_CBS_MASK … #define I40E_IEEE_ETS_WILLING_SHIFT … #define I40E_IEEE_ETS_WILLING_MASK … #define I40E_IEEE_ETS_PRIO_0_SHIFT … #define I40E_IEEE_ETS_PRIO_0_MASK … #define I40E_IEEE_ETS_PRIO_1_SHIFT … #define I40E_IEEE_ETS_PRIO_1_MASK … #define I40E_CEE_PGID_PRIO_0_SHIFT … #define I40E_CEE_PGID_PRIO_0_MASK … #define I40E_CEE_PGID_PRIO_1_SHIFT … #define I40E_CEE_PGID_PRIO_1_MASK … #define I40E_CEE_PGID_STRICT … /* Defines for IEEE TSA types */ #define I40E_IEEE_TSA_STRICT … #define I40E_IEEE_TSA_ETS … /* Defines for IEEE PFC TLV */ #define I40E_DCB_PFC_ENABLED … #define I40E_DCB_PFC_FORCED_NUM_TC … #define I40E_IEEE_PFC_CAP_SHIFT … #define I40E_IEEE_PFC_CAP_MASK … #define I40E_IEEE_PFC_MBC_SHIFT … #define I40E_IEEE_PFC_MBC_MASK … #define I40E_IEEE_PFC_WILLING_SHIFT … #define I40E_IEEE_PFC_WILLING_MASK … /* Defines for IEEE APP TLV */ #define I40E_IEEE_APP_SEL_SHIFT … #define I40E_IEEE_APP_SEL_MASK … #define I40E_IEEE_APP_PRIO_SHIFT … #define I40E_IEEE_APP_PRIO_MASK … /* TLV definitions for preparing MIB */ #define I40E_TLV_ID_CHASSIS_ID … #define I40E_TLV_ID_PORT_ID … #define I40E_TLV_ID_TIME_TO_LIVE … #define I40E_IEEE_TLV_ID_ETS_CFG … #define I40E_IEEE_TLV_ID_ETS_REC … #define I40E_IEEE_TLV_ID_PFC_CFG … #define I40E_IEEE_TLV_ID_APP_PRI … #define I40E_TLV_ID_END_OF_LLDPPDU … #define I40E_TLV_ID_START … #define I40E_IEEE_TLV_HEADER_LENGTH … #define I40E_IEEE_ETS_TLV_LENGTH … #define I40E_IEEE_PFC_TLV_LENGTH … #define I40E_IEEE_APP_TLV_LENGTH … /* Defines for default SW DCB config */ #define I40E_IEEE_DEFAULT_ETS_TCBW … #define I40E_IEEE_DEFAULT_ETS_WILLING … #define I40E_IEEE_DEFAULT_PFC_WILLING … #define I40E_IEEE_DEFAULT_NUM_APPS … #define I40E_IEEE_DEFAULT_APP_PRIO … #pragma pack(1) /* IEEE 802.1AB LLDP Organization specific TLV */ struct i40e_lldp_org_tlv { … }; struct i40e_cee_tlv_hdr { … }; struct i40e_cee_ctrl_tlv { … }; struct i40e_cee_feat_tlv { … }; struct i40e_cee_app_prio { … }; #pragma pack() enum i40e_get_fw_lldp_status_resp { … }; /* Data structures to pass for SW DCBX */ struct i40e_rx_pb_config { … }; enum i40e_dcb_arbiter_mode { … }; #define I40E_DCB_DEFAULT_MAX_EXPONENT … #define I40E_DEFAULT_PAUSE_TIME … #define I40E_MAX_FRAME_SIZE … #define I40E_DEVICE_RPB_SIZE … /* BitTimes (BT) conversion */ #define I40E_BT2KB(BT) … #define I40E_B2BT(BT) … #define I40E_BT2B(BT) … /* Max Frame(TC) = MFS(max) + MFS(TC) */ #define I40E_MAX_FRAME_TC(mfs_max, mfs_tc) … /* EEE Tx LPI Exit time in Bit Times */ #define I40E_EEE_TX_LPI_EXIT_TIME … /* PCI Round Trip Time in Bit Times */ #define I40E_PCIRTT_LINK_SPEED_10G … #define I40E_PCIRTT_BYTE_LINK_SPEED_20G … #define I40E_PCIRTT_BYTE_LINK_SPEED_40G … /* PFC Frame Delay Bit Times */ #define I40E_PFC_FRAME_DELAY … /* Worst case Cable (10GBase-T) Delay Bit Times */ #define I40E_CABLE_DELAY … /* Higher Layer Delay @10G Bit Times */ #define I40E_HIGHER_LAYER_DELAY_10G … /* Interface Delays in Bit Times */ /* TODO: Add for other link speeds 20G/40G/etc. */ #define I40E_INTERFACE_DELAY_10G_MAC_CONTROL … #define I40E_INTERFACE_DELAY_10G_MAC … #define I40E_INTERFACE_DELAY_10G_RS … #define I40E_INTERFACE_DELAY_XGXS … #define I40E_INTERFACE_DELAY_XAUI … #define I40E_INTERFACE_DELAY_10G_BASEX_PCS … #define I40E_INTERFACE_DELAY_10G_BASER_PCS … #define I40E_INTERFACE_DELAY_LX4_PMD … #define I40E_INTERFACE_DELAY_CX4_PMD … #define I40E_INTERFACE_DELAY_SERIAL_PMA … #define I40E_INTERFACE_DELAY_PMD … #define I40E_INTERFACE_DELAY_10G_BASET … /* Hardware RX DCB config related defines */ #define I40E_DCB_1_PORT_THRESHOLD … #define I40E_DCB_1_PORT_FIFO_SIZE … #define I40E_DCB_2_PORT_THRESHOLD_LOW_NUM_TC … #define I40E_DCB_2_PORT_FIFO_SIZE_LOW_NUM_TC … #define I40E_DCB_2_PORT_THRESHOLD_HIGH_NUM_TC … #define I40E_DCB_2_PORT_FIFO_SIZE_HIGH_NUM_TC … #define I40E_DCB_4_PORT_THRESHOLD_LOW_NUM_TC … #define I40E_DCB_4_PORT_FIFO_SIZE_LOW_NUM_TC … #define I40E_DCB_4_PORT_THRESHOLD_HIGH_NUM_TC … #define I40E_DCB_4_PORT_FIFO_SIZE_HIGH_NUM_TC … #define I40E_DCB_WATERMARK_START_FACTOR … /* delay values for with 10G BaseT in Bit Times */ #define I40E_INTERFACE_DELAY_10G_COPPER … #define I40E_DV_TC(mfs_max, mfs_tc) … static inline u32 I40E_STD_DV_TC(u32 mfs_max, u32 mfs_tc) { … } /* APIs for SW DCBX */ void i40e_dcb_hw_rx_fifo_config(struct i40e_hw *hw, enum i40e_dcb_arbiter_mode ets_mode, enum i40e_dcb_arbiter_mode non_ets_mode, u32 max_exponent, u8 lltc_map); void i40e_dcb_hw_rx_cmd_monitor_config(struct i40e_hw *hw, u8 num_tc, u8 num_ports); void i40e_dcb_hw_pfc_config(struct i40e_hw *hw, u8 pfc_en, u8 *prio_tc); void i40e_dcb_hw_set_num_tc(struct i40e_hw *hw, u8 num_tc); u8 i40e_dcb_hw_get_num_tc(struct i40e_hw *hw); void i40e_dcb_hw_rx_ets_bw_config(struct i40e_hw *hw, u8 *bw_share, u8 *mode, u8 *prio_type); void i40e_dcb_hw_rx_up2tc_config(struct i40e_hw *hw, u8 *prio_tc); void i40e_dcb_hw_calculate_pool_sizes(struct i40e_hw *hw, u8 num_ports, bool eee_enabled, u8 pfc_en, u32 *mfs_tc, struct i40e_rx_pb_config *pb_cfg); void i40e_dcb_hw_rx_pb_config(struct i40e_hw *hw, struct i40e_rx_pb_config *old_pb_cfg, struct i40e_rx_pb_config *new_pb_cfg); int i40e_get_dcbx_status(struct i40e_hw *hw, u16 *status); int i40e_lldp_to_dcb_config(u8 *lldpmib, struct i40e_dcbx_config *dcbcfg); int i40e_aq_get_dcb_config(struct i40e_hw *hw, u8 mib_type, u8 bridgetype, struct i40e_dcbx_config *dcbcfg); int i40e_get_dcb_config(struct i40e_hw *hw); int i40e_init_dcb(struct i40e_hw *hw, bool enable_mib_change); int i40e_get_fw_lldp_status(struct i40e_hw *hw, enum i40e_get_fw_lldp_status_resp *lldp_status); int i40e_set_dcb_config(struct i40e_hw *hw); int i40e_dcb_config_to_lldp(u8 *lldpmib, u16 *miblen, struct i40e_dcbx_config *dcbcfg); #endif /* _I40E_DCB_H_ */
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