/* SPDX-License-Identifier: GPL-2.0 */ /* Copyright(c) 2013 - 2018 Intel Corporation. */ #ifndef _I40E_TXRX_H_ #define _I40E_TXRX_H_ #include <net/xdp.h> #include "i40e_type.h" /* Interrupt Throttling and Rate Limiting Goodies */ #define I40E_DEFAULT_IRQ_WORK … /* The datasheet for the X710 and XL710 indicate that the maximum value for * the ITR is 8160usec which is then called out as 0xFF0 with a 2usec * resolution. 8160 is 0x1FE0 when written out in hex. So instead of storing * the register value which is divided by 2 lets use the actual values and * avoid an excessive amount of translation. */ #define I40E_ITR_DYNAMIC … #define I40E_ITR_MASK … #define I40E_MIN_ITR … #define I40E_ITR_20K … #define I40E_ITR_8K … #define I40E_MAX_ITR … #define ITR_TO_REG(setting) … #define ITR_REG_ALIGN(setting) … #define ITR_IS_DYNAMIC(setting) … #define I40E_ITR_RX_DEF … #define I40E_ITR_TX_DEF … /* 0x40 is the enable bit for interrupt rate limiting, and must be set if * the value of the rate limit is non-zero */ #define INTRL_ENA … #define I40E_MAX_INTRL … #define INTRL_REG_TO_USEC(intrl) … /** * i40e_intrl_usec_to_reg - convert interrupt rate limit to register * @intrl: interrupt rate limit to convert * * This function converts a decimal interrupt rate limit to the appropriate * register format expected by the firmware when setting interrupt rate limit. */ static inline u16 i40e_intrl_usec_to_reg(int intrl) { … } #define I40E_QUEUE_END_OF_LIST … /* this enum matches hardware bits and is meant to be used by DYN_CTLN * registers and QINT registers or more generally anywhere in the manual * mentioning ITR_INDX, ITR_NONE cannot be used as an index 'n' into any * register but instead is a special value meaning "don't update" ITR0/1/2. */ enum i40e_dyn_idx { … }; /* these are indexes into ITRN registers */ #define I40E_RX_ITR … #define I40E_TX_ITR … #define I40E_SW_ITR … /* Supported RSS offloads */ #define I40E_DEFAULT_RSS_HENA … #define I40E_DEFAULT_RSS_HENA_EXPANDED … #define i40e_pf_get_default_rss_hena(pf) … /* Supported Rx Buffer Sizes (a multiple of 128) */ #define I40E_RXBUFFER_256 … #define I40E_RXBUFFER_1536 … #define I40E_RXBUFFER_2048 … #define I40E_RXBUFFER_3072 … #define I40E_MAX_RXBUFFER … /* NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we * reserve 2 more, and skb_shared_info adds an additional 384 bytes more, * this adds up to 512 bytes of extra data meaning the smallest allocation * we could have is 1K. * i.e. RXBUFFER_256 --> 960 byte skb (size-1024 slab) * i.e. RXBUFFER_512 --> 1216 byte skb (size-2048 slab) */ #define I40E_RX_HDR_SIZE … #define I40E_PACKET_HDR_PAD … #define i40e_rx_desc … #define I40E_RX_DMA_ATTR … /* Attempt to maximize the headroom available for incoming frames. We * use a 2K buffer for receives and need 1536/1534 to store the data for * the frame. This leaves us with 512 bytes of room. From that we need * to deduct the space needed for the shared info and the padding needed * to IP align the frame. * * Note: For cache line sizes 256 or larger this value is going to end * up negative. In these cases we should fall back to the legacy * receive path. */ #if (PAGE_SIZE < 8192) #define I40E_2K_TOO_SMALL_WITH_PADDING … static inline int i40e_compute_pad(int rx_buf_len) { … } static inline int i40e_skb_pad(void) { … } #define I40E_SKB_PAD … #else #define I40E_2K_TOO_SMALL_WITH_PADDING … #define I40E_SKB_PAD … #endif /** * i40e_test_staterr - tests bits in Rx descriptor status and error fields * @rx_desc: pointer to receive descriptor (in le64 format) * @stat_err_bits: value to mask * * This function does some fast chicanery in order to return the * value of the mask which is really only used for boolean tests. * The status_error_len doesn't need to be shifted because it begins * at offset zero. */ static inline bool i40e_test_staterr(union i40e_rx_desc *rx_desc, const u64 stat_err_bits) { … } /* How many Rx Buffers do we bundle into one write to the hardware ? */ #define I40E_RX_BUFFER_WRITE … #define I40E_RX_NEXT_DESC(r, i, n) … #define I40E_MAX_BUFFER_TXD … #define I40E_MIN_TX_LEN … /* The size limit for a transmit buffer in a descriptor is (16K - 1). * In order to align with the read requests we will align the value to * the nearest 4K which represents our maximum read request size. */ #define I40E_MAX_READ_REQ_SIZE … #define I40E_MAX_DATA_PER_TXD … #define I40E_MAX_DATA_PER_TXD_ALIGNED … /** * i40e_txd_use_count - estimate the number of descriptors needed for Tx * @size: transmit request size in bytes * * Due to hardware alignment restrictions (4K alignment), we need to * assume that we can have no more than 12K of data per descriptor, even * though each descriptor can take up to 16K - 1 bytes of aligned memory. * Thus, we need to divide by 12K. But division is slow! Instead, * we decompose the operation into shifts and one relatively cheap * multiply operation. * * To divide by 12K, we first divide by 4K, then divide by 3: * To divide by 4K, shift right by 12 bits * To divide by 3, multiply by 85, then divide by 256 * (Divide by 256 is done by shifting right by 8 bits) * Finally, we add one to round up. Because 256 isn't an exact multiple of * 3, we'll underestimate near each multiple of 12K. This is actually more * accurate as we have 4K - 1 of wiggle room that we can fit into the last * segment. For our purposes this is accurate out to 1M which is orders of * magnitude greater than our largest possible GSO size. * * This would then be implemented as: * return (((size >> 12) * 85) >> 8) + 1; * * Since multiplication and division are commutative, we can reorder * operations into: * return ((size * 85) >> 20) + 1; */ static inline unsigned int i40e_txd_use_count(unsigned int size) { … } /* Tx Descriptors needed, worst case */ #define DESC_NEEDED … #define I40E_TX_FLAGS_HW_VLAN … #define I40E_TX_FLAGS_SW_VLAN … #define I40E_TX_FLAGS_TSO … #define I40E_TX_FLAGS_IPV4 … #define I40E_TX_FLAGS_IPV6 … #define I40E_TX_FLAGS_TSYN … #define I40E_TX_FLAGS_FD_SB … #define I40E_TX_FLAGS_UDP_TUNNEL … #define I40E_TX_FLAGS_VLAN_MASK … #define I40E_TX_FLAGS_VLAN_PRIO_MASK … #define I40E_TX_FLAGS_VLAN_PRIO_SHIFT … #define I40E_TX_FLAGS_VLAN_SHIFT … struct i40e_tx_buffer { … }; struct i40e_rx_buffer { … }; struct i40e_queue_stats { … }; struct i40e_tx_queue_stats { … }; struct i40e_rx_queue_stats { … }; enum i40e_ring_state { … }; /* some useful defines for virtchannel interface, which * is the only remaining user of header split */ #define I40E_RX_DTYPE_HEADER_SPLIT … #define I40E_RX_SPLIT_L2 … #define I40E_RX_SPLIT_IP … #define I40E_RX_SPLIT_TCP_UDP … #define I40E_RX_SPLIT_SCTP … /* struct that defines a descriptor ring, associated with a VSI */ struct i40e_ring { … } ____cacheline_internodealigned_in_smp; static inline bool ring_uses_build_skb(struct i40e_ring *ring) { … } static inline void set_ring_build_skb_enabled(struct i40e_ring *ring) { … } static inline void clear_ring_build_skb_enabled(struct i40e_ring *ring) { … } static inline bool ring_is_xdp(struct i40e_ring *ring) { … } static inline void set_ring_xdp(struct i40e_ring *ring) { … } #define I40E_ITR_ADAPTIVE_MIN_INC … #define I40E_ITR_ADAPTIVE_MIN_USECS … #define I40E_ITR_ADAPTIVE_MAX_USECS … #define I40E_ITR_ADAPTIVE_LATENCY … #define I40E_ITR_ADAPTIVE_BULK … struct i40e_ring_container { … }; /* iterator for handling rings in ring container */ #define i40e_for_each_ring(pos, head) … static inline unsigned int i40e_rx_pg_order(struct i40e_ring *ring) { … } #define i40e_rx_pg_size(_ring) … bool i40e_alloc_rx_buffers(struct i40e_ring *rxr, u16 cleaned_count); netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev); u16 i40e_lan_select_queue(struct net_device *netdev, struct sk_buff *skb, struct net_device *sb_dev); void i40e_clean_tx_ring(struct i40e_ring *tx_ring); void i40e_clean_rx_ring(struct i40e_ring *rx_ring); int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring); int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring); void i40e_free_tx_resources(struct i40e_ring *tx_ring); void i40e_free_rx_resources(struct i40e_ring *rx_ring); int i40e_napi_poll(struct napi_struct *napi, int budget); void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector); u32 i40e_get_tx_pending(struct i40e_ring *ring, bool in_sw); void i40e_detect_recover_hung(struct i40e_pf *pf); int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size); bool __i40e_chk_linearize(struct sk_buff *skb); int i40e_xdp_xmit(struct net_device *dev, int n, struct xdp_frame **frames, u32 flags); bool i40e_is_non_eop(struct i40e_ring *rx_ring, union i40e_rx_desc *rx_desc); /** * i40e_get_head - Retrieve head from head writeback * @tx_ring: tx ring to fetch head of * * Returns value of Tx ring head based on value stored * in head write-back location **/ static inline u32 i40e_get_head(struct i40e_ring *tx_ring) { … } /** * i40e_xmit_descriptor_count - calculate number of Tx descriptors needed * @skb: send buffer * * Returns number of data descriptors needed for this skb. Returns 0 to indicate * there is not enough descriptors available in this ring since we need at least * one descriptor. **/ static inline int i40e_xmit_descriptor_count(struct sk_buff *skb) { … } /** * i40e_maybe_stop_tx - 1st level check for Tx stop conditions * @tx_ring: the ring to be checked * @size: the size buffer we want to assure is available * * Returns 0 if stop is not needed **/ static inline int i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size) { … } /** * i40e_chk_linearize - Check if there are more than 8 fragments per packet * @skb: send buffer * @count: number of buffers used * * Note: Our HW can't scatter-gather more than 8 fragments to build * a packet on the wire and so we need to figure out the cases where we * need to linearize the skb. **/ static inline bool i40e_chk_linearize(struct sk_buff *skb, int count) { … } /** * txring_txq - Find the netdev Tx ring based on the i40e Tx ring * @ring: Tx ring to find the netdev equivalent of **/ static inline struct netdev_queue *txring_txq(const struct i40e_ring *ring) { … } #endif /* _I40E_TXRX_H_ */
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