// SPDX-License-Identifier: GPL-2.0 /* * FU740 DesignWare PCIe Controller integration * Copyright (C) 2019-2021 SiFive, Inc. * Paul Walmsley * Greentime Hu * * Based in part on the i.MX6 PCIe host controller shim which is: * * Copyright (C) 2013 Kosagi * https://www.kosagi.com */ #include <linux/clk.h> #include <linux/delay.h> #include <linux/gpio.h> #include <linux/gpio/consumer.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/pci.h> #include <linux/platform_device.h> #include <linux/resource.h> #include <linux/types.h> #include <linux/interrupt.h> #include <linux/iopoll.h> #include <linux/reset.h> #include "pcie-designware.h" #define to_fu740_pcie(x) … struct fu740_pcie { … }; #define SIFIVE_DEVICESRESETREG … #define PCIEX8MGMT_PERST_N … #define PCIEX8MGMT_APP_LTSSM_ENABLE … #define PCIEX8MGMT_APP_HOLD_PHY_RST … #define PCIEX8MGMT_DEVICE_TYPE … #define PCIEX8MGMT_PHY0_CR_PARA_ADDR … #define PCIEX8MGMT_PHY0_CR_PARA_RD_EN … #define PCIEX8MGMT_PHY0_CR_PARA_RD_DATA … #define PCIEX8MGMT_PHY0_CR_PARA_SEL … #define PCIEX8MGMT_PHY0_CR_PARA_WR_DATA … #define PCIEX8MGMT_PHY0_CR_PARA_WR_EN … #define PCIEX8MGMT_PHY0_CR_PARA_ACK … #define PCIEX8MGMT_PHY1_CR_PARA_ADDR … #define PCIEX8MGMT_PHY1_CR_PARA_RD_EN … #define PCIEX8MGMT_PHY1_CR_PARA_RD_DATA … #define PCIEX8MGMT_PHY1_CR_PARA_SEL … #define PCIEX8MGMT_PHY1_CR_PARA_WR_DATA … #define PCIEX8MGMT_PHY1_CR_PARA_WR_EN … #define PCIEX8MGMT_PHY1_CR_PARA_ACK … #define PCIEX8MGMT_PHY_CDR_TRACK_EN … #define PCIEX8MGMT_PHY_LOS_THRSHLD … #define PCIEX8MGMT_PHY_TERM_EN … #define PCIEX8MGMT_PHY_TERM_ACDC … #define PCIEX8MGMT_PHY_EN … #define PCIEX8MGMT_PHY_INIT_VAL … #define PCIEX8MGMT_PHY_LANEN_DIG_ASIC_RX_OVRD_IN_3 … #define PCIEX8MGMT_PHY_LANE_OFF … #define PCIEX8MGMT_PHY_LANE0_BASE … #define PCIEX8MGMT_PHY_LANE1_BASE … #define PCIEX8MGMT_PHY_LANE2_BASE … #define PCIEX8MGMT_PHY_LANE3_BASE … static void fu740_pcie_assert_reset(struct fu740_pcie *afp) { … } static void fu740_pcie_deassert_reset(struct fu740_pcie *afp) { … } static void fu740_pcie_power_on(struct fu740_pcie *afp) { … } static void fu740_pcie_drive_reset(struct fu740_pcie *afp) { … } static void fu740_phyregwrite(const uint8_t phy, const uint16_t addr, const uint16_t wrdata, struct fu740_pcie *afp) { … } static void fu740_pcie_init_phy(struct fu740_pcie *afp) { … } static int fu740_pcie_start_link(struct dw_pcie *pci) { … } static int fu740_pcie_host_init(struct dw_pcie_rp *pp) { … } static const struct dw_pcie_host_ops fu740_pcie_host_ops = …; static const struct dw_pcie_ops dw_pcie_ops = …; static int fu740_pcie_probe(struct platform_device *pdev) { … } static void fu740_pcie_shutdown(struct platform_device *pdev) { … } static const struct of_device_id fu740_pcie_of_match[] = …; static struct platform_driver fu740_pcie_driver = …; builtin_platform_driver(…) …;
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