/* SPDX-License-Identifier: GPL-2.0 */ /* Copyright (c) 2018, Intel Corporation. */ #ifndef _ICE_ADMINQ_CMD_H_ #define _ICE_ADMINQ_CMD_H_ /* This header file defines the Admin Queue commands, error codes and * descriptor format. It is shared between Firmware and Software. */ #define ICE_MAX_VSI … #define ICE_AQC_TOPO_MAX_LEVEL_NUM … #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX … struct ice_aqc_generic { … }; /* Get version (direct 0x0001) */ struct ice_aqc_get_ver { … }; /* Send driver version (indirect 0x0002) */ struct ice_aqc_driver_ver { … }; /* Queue Shutdown (direct 0x0003) */ struct ice_aqc_q_shutdown { … }; /* Request resource ownership (direct 0x0008) * Release resource ownership (direct 0x0009) */ struct ice_aqc_req_res { … }; /* Get function capabilities (indirect 0x000A) * Get device capabilities (indirect 0x000B) */ struct ice_aqc_list_caps { … }; /* Device/Function buffer entry, repeated per reported capability */ struct ice_aqc_list_caps_elem { … }; /* Manage MAC address, read command - indirect (0x0107) * This struct is also used for the response */ struct ice_aqc_manage_mac_read { … }; /* Response buffer format for manage MAC read command */ struct ice_aqc_manage_mac_read_resp { … }; /* Manage MAC address, write command - direct (0x0108) */ struct ice_aqc_manage_mac_write { … }; /* Clear PXE Command and response (direct 0x0110) */ struct ice_aqc_clear_pxe { … }; /* Get switch configuration (0x0200) */ struct ice_aqc_get_sw_cfg { … }; /* Each entry in the response buffer is of the following type: */ struct ice_aqc_get_sw_cfg_resp_elem { … }; /* Loopback port parameter mode values. */ enum ice_local_fwd_mode { … }; /* Set Port parameters, (direct, 0x0203) */ struct ice_aqc_set_port_params { … }; /* These resource type defines are used for all switch resource * commands where a resource type is required, such as: * Get Resource Allocation command (indirect 0x0204) * Allocate Resources command (indirect 0x0208) * Free Resources command (indirect 0x0209) * Get Allocated Resource Descriptors Command (indirect 0x020A) * Share Resource command (indirect 0x020B) */ #define ICE_AQC_RES_TYPE_VSI_LIST_REP … #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE … #define ICE_AQC_RES_TYPE_RECIPE … #define ICE_AQC_RES_TYPE_SWID … #define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK … #define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES … #define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES … #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID … #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_TCAM … #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID … #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM … #define ICE_AQC_RES_TYPE_FLAG_SHARED … #define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM … #define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX … #define ICE_AQC_RES_TYPE_FLAG_SUBSCRIBE_SHARED … #define ICE_AQC_RES_TYPE_FLAG_SUBSCRIBE_CTL … #define ICE_AQC_RES_TYPE_FLAG_DEDICATED … #define ICE_AQC_RES_TYPE_S … #define ICE_AQC_RES_TYPE_M … /* Allocate Resources command (indirect 0x0208) * Free Resources command (indirect 0x0209) * Share Resource command (indirect 0x020B) */ struct ice_aqc_alloc_free_res_cmd { … }; /* Resource descriptor */ struct ice_aqc_res_elem { … }; /* Buffer for Allocate/Free Resources commands */ struct ice_aqc_alloc_free_res_elem { … }; /* Request buffer for Set VLAN Mode AQ command (indirect 0x020C) */ struct ice_aqc_set_vlan_mode { … }; /* Response buffer for Get VLAN Mode AQ command (indirect 0x020D) */ struct ice_aqc_get_vlan_mode { … }; /* Add VSI (indirect 0x0210) * Update VSI (indirect 0x0211) * Get VSI (indirect 0x0212) * Free VSI (indirect 0x0213) */ struct ice_aqc_add_get_update_free_vsi { … }; /* Response descriptor for: * Add VSI (indirect 0x0210) * Update VSI (indirect 0x0211) * Free VSI (indirect 0x0213) */ struct ice_aqc_add_update_free_vsi_resp { … }; struct ice_aqc_vsi_props { … }; #define ICE_MAX_NUM_RECIPES … /* Add/Get Recipe (indirect 0x0290/0x0292) */ struct ice_aqc_add_get_recipe { … }; struct ice_aqc_recipe_content { … }; struct ice_aqc_recipe_data_elem { … }; /* Set/Get Recipes to Profile Association (direct 0x0291/0x0293) */ struct ice_aqc_recipe_to_profile { … }; static_assert(…); /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3) */ struct ice_aqc_sw_rules { … }; /* Add switch rule response: * Content of return buffer is same as the input buffer. The status field and * LUT index are updated as part of the response */ struct ice_aqc_sw_rules_elem_hdr { … } __packed __aligned(…); /* Add/Update/Get/Remove lookup Rx/Tx command/response entry * This structures describes the lookup rules and associated actions. "index" * is returned as part of a response to a successful Add command, and can be * used to identify the rule for Update/Get/Remove commands. */ struct ice_sw_rule_lkup_rx_tx { … } __packed __aligned(…); /* Add/Update/Remove large action command/response entry * "index" is returned as part of a response to a successful Add command, and * can be used to identify the action for Update/Get/Remove commands. */ struct ice_sw_rule_lg_act { … } __packed __aligned(…); /* Add/Update/Remove VSI list command/response entry * "index" is returned as part of a response to a successful Add command, and * can be used to identify the VSI list for Update/Get/Remove commands. */ struct ice_sw_rule_vsi_list { … } __packed __aligned(…); /* Query PFC Mode (direct 0x0302) * Set PFC Mode (direct 0x0303) */ struct ice_aqc_set_query_pfc_mode { … }; /* Get Default Topology (indirect 0x0400) */ struct ice_aqc_get_topo { … }; /* Get/Set Tx Topology (indirect 0x0418/0x0417) */ struct ice_aqc_get_set_tx_topo { … }; /* Update TSE (indirect 0x0403) * Get TSE (indirect 0x0404) * Add TSE (indirect 0x0401) * Delete TSE (indirect 0x040F) * Move TSE (indirect 0x0408) * Suspend Nodes (indirect 0x0409) * Resume Nodes (indirect 0x040A) */ struct ice_aqc_sched_elem_cmd { … }; struct ice_aqc_txsched_move_grp_info_hdr { … }; struct ice_aqc_move_elem { … }; struct ice_aqc_elem_info_bw { … }; struct ice_aqc_txsched_elem { … }; struct ice_aqc_txsched_elem_data { … }; struct ice_aqc_txsched_topo_grp_info_hdr { … }; struct ice_aqc_add_elem { … }; struct ice_aqc_get_topo_elem { … }; struct ice_aqc_delete_elem { … }; /* Query Port ETS (indirect 0x040E) * * This indirect command is used to query port TC node configuration. */ struct ice_aqc_query_port_ets { … }; struct ice_aqc_port_ets_elem { … }; /* Rate limiting profile for * Add RL profile (indirect 0x0410) * Query RL profile (indirect 0x0411) * Remove RL profile (indirect 0x0415) * These indirect commands acts on single or multiple * RL profiles with specified data. */ struct ice_aqc_rl_profile { … }; struct ice_aqc_rl_profile_elem { … }; /* Query Scheduler Resource Allocation (indirect 0x0412) * This indirect command retrieves the scheduler resources allocated by * EMP Firmware to the given PF. */ struct ice_aqc_query_txsched_res { … }; struct ice_aqc_generic_sched_props { … }; struct ice_aqc_layer_props { … }; struct ice_aqc_query_txsched_res_resp { … }; /* Get PHY capabilities (indirect 0x0600) */ struct ice_aqc_get_phy_caps { … }; /* This is #define of PHY type (Extended): * The first set of defines is for phy_type_low. */ #define ICE_PHY_TYPE_LOW_100BASE_TX … #define ICE_PHY_TYPE_LOW_100M_SGMII … #define ICE_PHY_TYPE_LOW_1000BASE_T … #define ICE_PHY_TYPE_LOW_1000BASE_SX … #define ICE_PHY_TYPE_LOW_1000BASE_LX … #define ICE_PHY_TYPE_LOW_1000BASE_KX … #define ICE_PHY_TYPE_LOW_1G_SGMII … #define ICE_PHY_TYPE_LOW_2500BASE_T … #define ICE_PHY_TYPE_LOW_2500BASE_X … #define ICE_PHY_TYPE_LOW_2500BASE_KX … #define ICE_PHY_TYPE_LOW_5GBASE_T … #define ICE_PHY_TYPE_LOW_5GBASE_KR … #define ICE_PHY_TYPE_LOW_10GBASE_T … #define ICE_PHY_TYPE_LOW_10G_SFI_DA … #define ICE_PHY_TYPE_LOW_10GBASE_SR … #define ICE_PHY_TYPE_LOW_10GBASE_LR … #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 … #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC … #define ICE_PHY_TYPE_LOW_10G_SFI_C2C … #define ICE_PHY_TYPE_LOW_25GBASE_T … #define ICE_PHY_TYPE_LOW_25GBASE_CR … #define ICE_PHY_TYPE_LOW_25GBASE_CR_S … #define ICE_PHY_TYPE_LOW_25GBASE_CR1 … #define ICE_PHY_TYPE_LOW_25GBASE_SR … #define ICE_PHY_TYPE_LOW_25GBASE_LR … #define ICE_PHY_TYPE_LOW_25GBASE_KR … #define ICE_PHY_TYPE_LOW_25GBASE_KR_S … #define ICE_PHY_TYPE_LOW_25GBASE_KR1 … #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC … #define ICE_PHY_TYPE_LOW_25G_AUI_C2C … #define ICE_PHY_TYPE_LOW_40GBASE_CR4 … #define ICE_PHY_TYPE_LOW_40GBASE_SR4 … #define ICE_PHY_TYPE_LOW_40GBASE_LR4 … #define ICE_PHY_TYPE_LOW_40GBASE_KR4 … #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC … #define ICE_PHY_TYPE_LOW_40G_XLAUI … #define ICE_PHY_TYPE_LOW_50GBASE_CR2 … #define ICE_PHY_TYPE_LOW_50GBASE_SR2 … #define ICE_PHY_TYPE_LOW_50GBASE_LR2 … #define ICE_PHY_TYPE_LOW_50GBASE_KR2 … #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC … #define ICE_PHY_TYPE_LOW_50G_LAUI2 … #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC … #define ICE_PHY_TYPE_LOW_50G_AUI2 … #define ICE_PHY_TYPE_LOW_50GBASE_CP … #define ICE_PHY_TYPE_LOW_50GBASE_SR … #define ICE_PHY_TYPE_LOW_50GBASE_FR … #define ICE_PHY_TYPE_LOW_50GBASE_LR … #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 … #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC … #define ICE_PHY_TYPE_LOW_50G_AUI1 … #define ICE_PHY_TYPE_LOW_100GBASE_CR4 … #define ICE_PHY_TYPE_LOW_100GBASE_SR4 … #define ICE_PHY_TYPE_LOW_100GBASE_LR4 … #define ICE_PHY_TYPE_LOW_100GBASE_KR4 … #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC … #define ICE_PHY_TYPE_LOW_100G_CAUI4 … #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC … #define ICE_PHY_TYPE_LOW_100G_AUI4 … #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 … #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 … #define ICE_PHY_TYPE_LOW_100GBASE_CP2 … #define ICE_PHY_TYPE_LOW_100GBASE_SR2 … #define ICE_PHY_TYPE_LOW_100GBASE_DR … #define ICE_PHY_TYPE_LOW_MAX_INDEX … /* The second set of defines is for phy_type_high. */ #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 … #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC … #define ICE_PHY_TYPE_HIGH_100G_CAUI2 … #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC … #define ICE_PHY_TYPE_HIGH_100G_AUI2 … #define ICE_PHY_TYPE_HIGH_200G_CR4_PAM4 … #define ICE_PHY_TYPE_HIGH_200G_SR4 … #define ICE_PHY_TYPE_HIGH_200G_FR4 … #define ICE_PHY_TYPE_HIGH_200G_LR4 … #define ICE_PHY_TYPE_HIGH_200G_DR4 … #define ICE_PHY_TYPE_HIGH_200G_KR4_PAM4 … #define ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC … #define ICE_PHY_TYPE_HIGH_200G_AUI4 … #define ICE_PHY_TYPE_HIGH_MAX_INDEX … struct ice_aqc_get_phy_caps_data { … }; /* Set PHY capabilities (direct 0x0601) * NOTE: This command must be followed by setup link and restart auto-neg */ struct ice_aqc_set_phy_cfg { … }; /* Set PHY config command data structure */ struct ice_aqc_set_phy_cfg_data { … }; /* Set MAC Config command data structure (direct 0x0603) */ struct ice_aqc_set_mac_cfg { … }; /* Restart AN command data structure (direct 0x0605) * Also used for response, with only the lport_num field present. */ struct ice_aqc_restart_an { … }; /* Get link status (indirect 0x0607), also used for Link Status Event */ struct ice_aqc_get_link_status { … }; /* Get link status response data structure, also used for Link Status Event */ struct ice_aqc_get_link_status_data { … } __packed; /* Set event mask command (direct 0x0613) */ struct ice_aqc_set_event_mask { … }; /* Set MAC Loopback command (direct 0x0620) */ struct ice_aqc_set_mac_lb { … }; /* Set PHY recovered clock output (direct 0x0630) */ struct ice_aqc_set_phy_rec_clk_out { … }; /* Get PHY recovered clock output (direct 0x0631) */ struct ice_aqc_get_phy_rec_clk_out { … }; /* Get sensor reading (direct 0x0632) */ struct ice_aqc_get_sensor_reading { … }; /* Get sensor reading response (direct 0x0632) */ struct ice_aqc_get_sensor_reading_resp { … }; /* DNL call command (indirect 0x0682) * Struct is used for both command and response */ struct ice_aqc_dnl_call_command { … }; struct ice_aqc_dnl_equa_param { … }; struct ice_aqc_dnl_equa_respon { … }; /* DNL call command/response buffer (indirect 0x0682) */ struct ice_aqc_dnl_call { … }; struct ice_aqc_link_topo_params { … }; struct ice_aqc_link_topo_addr { … }; /* Get Link Topology Handle (direct, 0x06E0) */ struct ice_aqc_get_link_topo { … }; /* Read/Write I2C (direct, 0x06E2/0x06E3) */ struct ice_aqc_i2c { … }; /* Read I2C Response (direct, 0x06E2) */ struct ice_aqc_read_i2c_resp { … }; /* Set Port Identification LED (direct, 0x06E9) */ struct ice_aqc_set_port_id_led { … }; /* Get Port Options (indirect, 0x06EA) */ struct ice_aqc_get_port_options { … }; struct ice_aqc_get_port_options_elem { … }; /* Set Port Option (direct, 0x06EB) */ struct ice_aqc_set_port_option { … }; /* Set/Get GPIO (direct, 0x06EC/0x06ED) */ struct ice_aqc_gpio { … }; /* Read/Write SFF EEPROM command (indirect 0x06EE) */ struct ice_aqc_sff_eeprom { … }; /* NVM Read command (indirect 0x0701) * NVM Erase commands (direct 0x0702) * NVM Update commands (indirect 0x0703) */ struct ice_aqc_nvm { … }; #define ICE_AQC_NVM_START_POINT … #define ICE_AQC_NVM_TX_TOPO_MOD_ID … struct ice_aqc_nvm_tx_topo_user_sel { … }; /* NVM Checksum Command (direct, 0x0706) */ struct ice_aqc_nvm_checksum { … }; /* Used for NVM Set Package Data command - 0x070A */ struct ice_aqc_nvm_pkg_data { … }; /* Used for Pass Component Table command - 0x070B */ struct ice_aqc_nvm_pass_comp_tbl { … }; struct ice_aqc_nvm_comp_tbl { … } __packed; /* Send to PF command (indirect 0x0801) ID is only used by PF * * Send to VF command (indirect 0x0802) ID is only used by PF * */ struct ice_aqc_pf_vf_msg { … }; /* Get LLDP MIB (indirect 0x0A00) * Note: This is also used by the LLDP MIB Change Event (0x0A01) * as the format is the same. */ struct ice_aqc_lldp_get_mib { … }; /* Configure LLDP MIB Change Event (direct 0x0A01) */ /* For MIB Change Event use ice_aqc_lldp_get_mib structure above */ struct ice_aqc_lldp_set_mib_change { … }; /* Stop LLDP (direct 0x0A05) */ struct ice_aqc_lldp_stop { … }; /* Start LLDP (direct 0x0A06) */ struct ice_aqc_lldp_start { … }; /* Get CEE DCBX Oper Config (0x0A07) * The command uses the generic descriptor struct and * returns the struct below as an indirect response. */ struct ice_aqc_get_cee_dcb_cfg_resp { … }; /* Set Local LLDP MIB (indirect 0x0A08) * Used to replace the local MIB of a given LLDP agent. e.g. DCBX */ struct ice_aqc_lldp_set_local_mib { … }; /* Stop/Start LLDP Agent (direct 0x0A09) * Used for stopping/starting specific LLDP agent. e.g. DCBX. * The same structure is used for the response, with the command field * being used as the status field. */ struct ice_aqc_lldp_stop_start_specific_agent { … }; /* LLDP Filter Control (direct 0x0A0A) */ struct ice_aqc_lldp_filter_ctrl { … }; #define ICE_AQC_RSS_VSI_VALID … /* Get/Set RSS key (indirect 0x0B04/0x0B02) */ struct ice_aqc_get_set_rss_key { … }; #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE … #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE … #define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE … struct ice_aqc_get_set_rss_keys { … }; enum ice_lut_type { … }; enum ice_lut_size { … }; /* enum ice_aqc_lut_flags combines constants used to fill * &ice_aqc_get_set_rss_lut ::flags, which is an amalgamation of global LUT ID, * LUT size and LUT type, last of which does not need neither shift nor mask. */ enum ice_aqc_lut_flags { … }; /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */ struct ice_aqc_get_set_rss_lut { … }; /* Sideband Control Interface Commands */ /* Neighbor Device Request (indirect 0x0C00); also used for the response. */ struct ice_aqc_neigh_dev_req { … }; /* Add Tx LAN Queues (indirect 0x0C30) */ struct ice_aqc_add_txqs { … }; /* This is the descriptor of each queue entry for the Add Tx LAN Queues * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp. */ struct ice_aqc_add_txqs_perq { … }; /* The format of the command buffer for Add Tx LAN Queues (0x0C30) * is an array of the following structs. Please note that the length of * each struct ice_aqc_add_tx_qgrp is variable due * to the variable number of queues in each group! */ struct ice_aqc_add_tx_qgrp { … }; /* Disable Tx LAN Queues (indirect 0x0C31) */ struct ice_aqc_dis_txqs { … }; /* The buffer for Disable Tx LAN Queues (indirect 0x0C31) * contains the following structures, arrayed one after the * other. * Note: Since the q_id is 16 bits wide, if the * number of queues is even, then 2 bytes of alignment MUST be * added before the start of the next group, to allow correct * alignment of the parent_teid field. */ struct ice_aqc_dis_txq_item { … } __packed; /* Move/Reconfigure Tx queue (indirect 0x0C32) */ struct ice_aqc_cfg_txqs { … }; /* Per Q struct for Move/Reconfigure Tx LAN Queues (indirect 0x0C32) */ struct ice_aqc_cfg_txq_perq { … }; /* The buffer for Move/Reconfigure Tx LAN Queues (indirect 0x0C32) */ struct ice_aqc_cfg_txqs_buf { … }; /* Add Tx RDMA Queue Set (indirect 0x0C33) */ struct ice_aqc_add_rdma_qset { … }; /* This is the descriptor of each Qset entry for the Add Tx RDMA Queue Set * command (0x0C33). Only used within struct ice_aqc_add_rdma_qset. */ struct ice_aqc_add_tx_rdma_qset_entry { … }; /* The format of the command buffer for Add Tx RDMA Queue Set(0x0C33) * is an array of the following structs. Please note that the length of * each struct ice_aqc_add_rdma_qset is variable due to the variable * number of queues in each group! */ struct ice_aqc_add_rdma_qset_data { … }; /* Download Package (indirect 0x0C40) */ /* Also used for Update Package (indirect 0x0C41 and 0x0C42) */ struct ice_aqc_download_pkg { … }; struct ice_aqc_download_pkg_resp { … }; /* Get Package Info List (indirect 0x0C43) */ struct ice_aqc_get_pkg_info_list { … }; /* Version format for packages */ struct ice_pkg_ver { … }; #define ICE_PKG_NAME_SIZE … #define ICE_SEG_ID_SIZE … #define ICE_SEG_NAME_SIZE … struct ice_aqc_get_pkg_info { … }; /* Get Package Info List response buffer format (0x0C43) */ struct ice_aqc_get_pkg_info_resp { … }; /* Get CGU abilities command response data structure (indirect 0x0C61) */ struct ice_aqc_get_cgu_abilities { … }; /* Set CGU input config (direct 0x0C62) */ struct ice_aqc_set_cgu_input_config { … }; /* Get CGU input config response descriptor structure (direct 0x0C63) */ struct ice_aqc_get_cgu_input_config { … }; /* Set CGU output config (direct 0x0C64) */ struct ice_aqc_set_cgu_output_config { … }; /* Get CGU output config (direct 0x0C65) */ struct ice_aqc_get_cgu_output_config { … }; /* Get CGU DPLL status (direct 0x0C66) */ struct ice_aqc_get_cgu_dpll_status { … }; /* Set CGU DPLL config (direct 0x0C67) */ struct ice_aqc_set_cgu_dpll_config { … }; /* Set CGU reference priority (direct 0x0C68) */ struct ice_aqc_set_cgu_ref_prio { … }; /* Get CGU reference priority (direct 0x0C69) */ struct ice_aqc_get_cgu_ref_prio { … }; /* Get CGU info (direct 0x0C6A) */ struct ice_aqc_get_cgu_info { … }; /* Driver Shared Parameters (direct, 0x0C90) */ struct ice_aqc_driver_shared_params { … }; /* Lan Queue Overflow Event (direct, 0x1001) */ struct ice_aqc_event_lan_overflow { … }; enum ice_aqc_fw_logging_mod { … }; /* Set FW Logging configuration (indirect 0xFF30) * Register for FW Logging (indirect 0xFF31) * Query FW Logging (indirect 0xFF32) * FW Log Event (indirect 0xFF33) */ struct ice_aqc_fw_log { … }; /* Response Buffer for: * Set Firmware Logging Configuration (0xFF30) * Query FW Logging (0xFF32) */ struct ice_aqc_fw_log_cfg_resp { … }; /** * struct ice_aq_desc - Admin Queue (AQ) descriptor * @flags: ICE_AQ_FLAG_* flags * @opcode: AQ command opcode * @datalen: length in bytes of indirect/external data buffer * @retval: return value from firmware * @cookie_high: opaque data high-half * @cookie_low: opaque data low-half * @params: command-specific parameters * * Descriptor format for commands the driver posts on the Admin Transmit Queue * (ATQ). The firmware writes back onto the command descriptor and returns * the result of the command. Asynchronous events that are not an immediate * result of the command are written to the Admin Receive Queue (ARQ) using * the same descriptor format. Descriptors are in little-endian notation with * 32-bit words. */ struct ice_aq_desc { … }; /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */ #define ICE_AQ_LG_BUF … #define ICE_AQ_FLAG_DD_S … #define ICE_AQ_FLAG_CMP_S … #define ICE_AQ_FLAG_ERR_S … #define ICE_AQ_FLAG_LB_S … #define ICE_AQ_FLAG_RD_S … #define ICE_AQ_FLAG_BUF_S … #define ICE_AQ_FLAG_SI_S … #define ICE_AQ_FLAG_DD … #define ICE_AQ_FLAG_CMP … #define ICE_AQ_FLAG_ERR … #define ICE_AQ_FLAG_LB … #define ICE_AQ_FLAG_RD … #define ICE_AQ_FLAG_BUF … #define ICE_AQ_FLAG_SI … /* error codes */ enum ice_aq_err { … }; /* Admin Queue command opcodes */ enum ice_adminq_opc { … }; #endif /* _ICE_ADMINQ_CMD_H_ */
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