/* SPDX-License-Identifier: GPL-2.0 */ /* Copyright (c) 2018, Intel Corporation. */ #ifndef _ICE_CONTROLQ_H_ #define _ICE_CONTROLQ_H_ #include "ice_adminq_cmd.h" /* Maximum buffer lengths for all control queue types */ #define ICE_AQ_MAX_BUF_LEN … #define ICE_MBXQ_MAX_BUF_LEN … #define ICE_SBQ_MAX_BUF_LEN … #define ICE_CTL_Q_DESC(R, i) … #define ICE_CTL_Q_DESC_UNUSED(R) … /* Defines that help manage the driver vs FW API checks. * Take a look at ice_aq_ver_check in ice_controlq.c for actual usage. */ #define EXP_FW_API_VER_MAJOR_E810 … #define EXP_FW_API_VER_MINOR_E810 … #define EXP_FW_API_VER_MAJOR_E830 … #define EXP_FW_API_VER_MINOR_E830 … #define EXP_FW_API_VER_MAJOR_BY_MAC(hw) … #define EXP_FW_API_VER_MINOR_BY_MAC(hw) … /* Different control queue types: These are mainly for SW consumption. */ enum ice_ctl_q { … }; /* Control Queue timeout settings - max delay 1s */ #define ICE_CTL_Q_SQ_CMD_TIMEOUT … #define ICE_CTL_Q_ADMIN_INIT_TIMEOUT … #define ICE_CTL_Q_ADMIN_INIT_MSEC … struct ice_ctl_q_ring { … }; /* sq transaction details */ struct ice_sq_cd { … }; /* rq event information */ struct ice_rq_event_info { … }; /* Control Queue information */ struct ice_ctl_q_info { … }; #endif /* _ICE_CONTROLQ_H_ */
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