/* SPDX-License-Identifier: GPL-2.0 */ /* Copyright (c) 2018-2023, Intel Corporation. */ #ifndef _ICE_TYPE_H_ #define _ICE_TYPE_H_ #define ICE_BYTES_PER_WORD … #define ICE_BYTES_PER_DWORD … #define ICE_CHNL_MAX_TC … #include "ice_hw_autogen.h" #include "ice_devids.h" #include "ice_osdep.h" #include "ice_controlq.h" #include "ice_lan_tx_rx.h" #include "ice_flex_type.h" #include "ice_protocol_type.h" #include "ice_sbq_cmd.h" #include "ice_vlan_mode.h" #include "ice_fwlog.h" static inline bool ice_is_tc_ena(unsigned long bitmap, u8 tc) { … } static inline u64 round_up_64bit(u64 a, u32 b) { … } static inline u32 ice_round_to_num(u32 N, u32 R) { … } /* Driver always calls main vsi_handle first */ #define ICE_MAIN_VSI_HANDLE … /* debug masks - set these bits in hw->debug_mask to control output */ #define ICE_DBG_INIT … #define ICE_DBG_FW_LOG … #define ICE_DBG_LINK … #define ICE_DBG_PHY … #define ICE_DBG_QCTX … #define ICE_DBG_NVM … #define ICE_DBG_LAN … #define ICE_DBG_FLOW … #define ICE_DBG_SW … #define ICE_DBG_SCHED … #define ICE_DBG_RDMA … #define ICE_DBG_PKG … #define ICE_DBG_RES … #define ICE_DBG_PTP … #define ICE_DBG_AQ_MSG … #define ICE_DBG_AQ_DESC … #define ICE_DBG_AQ_DESC_BUF … #define ICE_DBG_AQ_CMD … #define ICE_DBG_AQ … #define ICE_DBG_PARSER … #define ICE_DBG_USER … enum ice_aq_res_ids { … }; enum ice_fec_stats_types { … }; /* FW update timeout definitions are in milliseconds */ #define ICE_NVM_TIMEOUT … #define ICE_CHANGE_LOCK_TIMEOUT … #define ICE_GLOBAL_CFG_LOCK_TIMEOUT … enum ice_aq_res_access_type { … }; struct ice_driver_ver { … }; enum ice_fc_mode { … }; enum ice_phy_cache_mode { … }; enum ice_fec_mode { … }; struct ice_phy_cache_mode_data { … }; enum ice_set_fc_aq_failures { … }; /* Various MAC types */ enum ice_mac_type { … }; /* Media Types */ enum ice_media_type { … }; enum ice_vsi_type { … }; struct ice_link_status { … }; /* Different reset sources for which a disable queue AQ call has to be made in * order to clean the Tx scheduler as a part of the reset */ enum ice_disq_rst_src { … }; /* PHY info such as phy_type, etc... */ struct ice_phy_info { … }; /* protocol enumeration for filters */ enum ice_fltr_ptype { … }; enum ice_fd_hw_seg { … }; /* 1 ICE_VSI_PF + 1 ICE_VSI_CTRL + ICE_CHNL_MAX_TC */ #define ICE_MAX_FDIR_VSI_PER_FILTER … struct ice_fd_hw_prof { … }; /* Common HW capabilities for SW use */ struct ice_hw_common_caps { … }; /* IEEE 1588 TIME_SYNC specific info */ /* Function specific definitions */ #define ICE_TS_FUNC_ENA_M … #define ICE_TS_SRC_TMR_OWND_M … #define ICE_TS_TMR_ENA_M … #define ICE_TS_TMR_IDX_OWND_S … #define ICE_TS_TMR_IDX_OWND_M … #define ICE_TS_CLK_FREQ_S … #define ICE_TS_CLK_FREQ_M … #define ICE_TS_CLK_SRC_S … #define ICE_TS_CLK_SRC_M … #define ICE_TS_TMR_IDX_ASSOC_S … #define ICE_TS_TMR_IDX_ASSOC_M … /* TIME_REF clock rate specification */ enum ice_time_ref_freq { … }; /* Clock source specification */ enum ice_clk_src { … }; struct ice_ts_func_info { … }; /* Device specific definitions */ #define ICE_TS_TMR0_OWNR_M … #define ICE_TS_TMR0_OWND_M … #define ICE_TS_TMR1_OWNR_S … #define ICE_TS_TMR1_OWNR_M … #define ICE_TS_TMR1_OWND_M … #define ICE_TS_DEV_ENA_M … #define ICE_TS_TMR0_ENA_M … #define ICE_TS_TMR1_ENA_M … #define ICE_TS_LL_TX_TS_READ_M … #define ICE_TS_LL_TX_TS_INT_READ_M … struct ice_ts_dev_info { … }; #define ICE_NAC_TOPO_PRIMARY_M … #define ICE_NAC_TOPO_DUAL_M … #define ICE_NAC_TOPO_ID_M … struct ice_nac_topology { … }; /* Function specific capabilities */ struct ice_hw_func_caps { … }; #define ICE_SENSOR_SUPPORT_E810_INT_TEMP_BIT … /* Device wide capabilities */ struct ice_hw_dev_caps { … }; /* MAC info */ struct ice_mac_info { … }; /* Reset types used to determine which kind of reset was requested. These * defines match what the RESET_TYPE field of the GLGEN_RSTAT register. * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register * because its reset source is different than the other types listed. */ enum ice_reset_req { … }; /* Bus parameters */ struct ice_bus_info { … }; /* Flow control (FC) parameters */ struct ice_fc_info { … }; /* Option ROM version information */ struct ice_orom_info { … }; /* NVM version information */ struct ice_nvm_info { … }; /* netlist version information */ struct ice_netlist_info { … }; /* Enumeration of possible flash banks for the NVM, OROM, and Netlist modules * of the flash image. */ enum ice_flash_bank { … }; /* Enumeration of which flash bank is desired to read from, either the active * bank or the inactive bank. Used to abstract 1st and 2nd bank notion from * code which just wants to read the active or inactive flash bank. */ enum ice_bank_select { … }; /* information for accessing NVM, OROM, and Netlist flash banks */ struct ice_bank_info { … }; /* Flash Chip Information */ struct ice_flash_info { … }; struct ice_link_default_override_tlv { … }; #define ICE_NVM_VER_LEN … /* Max number of port to queue branches w.r.t topology */ #define ICE_MAX_TRAFFIC_CLASS … #define ICE_TXSCHED_MAX_BRANCHES … #define ice_for_each_traffic_class(_i) … /* ICE_DFLT_AGG_ID means that all new VM(s)/VSI node connects * to driver defined policy for default aggregator */ #define ICE_INVAL_TEID … #define ICE_DFLT_AGG_ID … struct ice_sched_node { … }; /* Access Macros for Tx Sched Elements data */ #define ICE_TXSCHED_GET_NODE_TEID(x) … /* The aggregator type determines if identifier is for a VSI group, * aggregator group, aggregator of queues, or queue group. */ enum ice_agg_type { … }; /* Rate limit types */ enum ice_rl_type { … }; #define ICE_SCHED_MIN_BW … #define ICE_SCHED_MAX_BW … #define ICE_SCHED_DFLT_BW … #define ICE_SCHED_DFLT_RL_PROF_ID … #define ICE_SCHED_NO_SHARED_RL_PROF_ID … #define ICE_SCHED_DFLT_BW_WT … #define ICE_SCHED_INVAL_PROF_ID … #define ICE_SCHED_DFLT_BURST_SIZE … #define ICE_MAX_PORT_PER_PCI_DEV … /* Data structure for saving BW information */ enum ice_bw_type { … }; struct ice_bw { … }; struct ice_bw_type_info { … }; /* VSI queue context structure for given TC */ struct ice_q_ctx { … }; /* VSI type list entry to locate corresponding VSI/aggregator nodes */ struct ice_sched_vsi_info { … }; /* driver defines the policy */ struct ice_sched_tx_policy { … }; /* CEE or IEEE 802.1Qaz ETS Configuration data */ struct ice_dcb_ets_cfg { … }; /* CEE or IEEE 802.1Qaz PFC Configuration data */ struct ice_dcb_pfc_cfg { … }; /* CEE or IEEE 802.1Qaz Application Priority data */ struct ice_dcb_app_priority_table { … }; #define ICE_MAX_USER_PRIORITY … #define ICE_DCBX_MAX_APPS … #define ICE_DSCP_NUM_VAL … #define ICE_LLDPDU_SIZE … #define ICE_TLV_STATUS_OPER … #define ICE_TLV_STATUS_SYNC … #define ICE_TLV_STATUS_ERR … #define ICE_APP_PROT_ID_ISCSI_860 … #define ICE_APP_SEL_ETHTYPE … #define ICE_APP_SEL_TCPIP … #define ICE_CEE_APP_SEL_ETHTYPE … #define ICE_SR_LINK_DEFAULT_OVERRIDE_PTR … #define ICE_CEE_APP_SEL_TCPIP … struct ice_dcbx_cfg { … }; struct ice_qos_cfg { … }; struct ice_port_info { … }; struct ice_switch_info { … }; /* Enum defining the different states of the mailbox snapshot in the * PF-VF mailbox overflow detection algorithm. The snapshot can be in * states: * 1. ICE_MAL_VF_DETECT_STATE_NEW_SNAPSHOT - generate a new static snapshot * within the mailbox buffer. * 2. ICE_MAL_VF_DETECT_STATE_TRAVERSE - iterate through the mailbox snaphot * 3. ICE_MAL_VF_DETECT_STATE_DETECT - track the messages sent per VF via the * mailbox and mark any VFs sending more messages than the threshold limit set. * 4. ICE_MAL_VF_DETECT_STATE_INVALID - Invalid mailbox state set to 0xFFFFFFFF. */ enum ice_mbx_snapshot_state { … }; /* Structure to hold information of the static snapshot and the mailbox * buffer data used to generate and track the snapshot. * 1. state: the state of the mailbox snapshot in the malicious VF * detection state handler ice_mbx_vf_state_handler() * 2. head: head of the mailbox snapshot in a circular mailbox buffer * 3. tail: tail of the mailbox snapshot in a circular mailbox buffer * 4. num_iterations: number of messages traversed in circular mailbox buffer * 5. num_msg_proc: number of messages processed in mailbox * 6. num_pending_arq: number of pending asynchronous messages * 7. max_num_msgs_mbx: maximum messages in mailbox for currently * serviced work item or interrupt. */ struct ice_mbx_snap_buffer_data { … }; /* Structure used to track a single VF's messages on the mailbox: * 1. list_entry: linked list entry node * 2. msg_count: the number of asynchronous messages sent by this VF * 3. malicious: whether this VF has been detected as malicious before */ struct ice_mbx_vf_info { … }; /* Structure to hold data relevant to the captured static snapshot * of the PF-VF mailbox. */ struct ice_mbx_snapshot { … }; /* Structure to hold data to be used for capturing or updating a * static snapshot. * 1. num_msg_proc: number of messages processed in mailbox * 2. num_pending_arq: number of pending asynchronous messages * 3. max_num_msgs_mbx: maximum messages in mailbox for currently * serviced work item or interrupt. * 4. async_watermark_val: An upper threshold set by caller to determine * if the pending arq count is large enough to assume that there is * the possibility of a mailicious VF. */ struct ice_mbx_data { … }; #define ICE_PORTS_PER_QUAD … #define ICE_GET_QUAD_NUM(port) … struct ice_eth56g_params { … }; ice_phy_params; /* PHY model */ enum ice_phy_model { … }; /* Global Link Topology */ enum ice_global_link_topo { … }; struct ice_ptp_hw { … }; /* Port hardware description */ struct ice_hw { … }; /* Statistics collected by each port, VSI, VEB, and S-channel */ struct ice_eth_stats { … }; #define ICE_MAX_UP … /* Statistics collected by the MAC */ struct ice_hw_port_stats { … }; enum ice_sw_fwd_act_type { … }; struct ice_aq_get_set_rss_lut_params { … }; /* Checksum and Shadow RAM pointers */ #define ICE_SR_NVM_CTRL_WORD … #define ICE_SR_BOOT_CFG_PTR … #define ICE_SR_NVM_WOL_CFG … #define ICE_NVM_OROM_VER_OFF … #define ICE_SR_PBA_BLOCK_PTR … #define ICE_SR_NVM_DEV_STARTER_VER … #define ICE_SR_NVM_EETRACK_LO … #define ICE_SR_NVM_EETRACK_HI … #define ICE_NVM_VER_LO_SHIFT … #define ICE_NVM_VER_LO_MASK … #define ICE_NVM_VER_HI_SHIFT … #define ICE_NVM_VER_HI_MASK … #define ICE_OROM_VER_PATCH_SHIFT … #define ICE_OROM_VER_PATCH_MASK … #define ICE_OROM_VER_BUILD_SHIFT … #define ICE_OROM_VER_BUILD_MASK … #define ICE_OROM_VER_SHIFT … #define ICE_OROM_VER_MASK … #define ICE_SR_PFA_PTR … #define ICE_SR_1ST_NVM_BANK_PTR … #define ICE_SR_NVM_BANK_SIZE … #define ICE_SR_1ST_OROM_BANK_PTR … #define ICE_SR_OROM_BANK_SIZE … #define ICE_SR_NETLIST_BANK_PTR … #define ICE_SR_NETLIST_BANK_SIZE … #define ICE_SR_SECTOR_SIZE_IN_WORDS … /* CSS Header words */ #define ICE_NVM_CSS_HDR_LEN_L … #define ICE_NVM_CSS_HDR_LEN_H … #define ICE_NVM_CSS_SREV_L … #define ICE_NVM_CSS_SREV_H … /* Length of Authentication header section in words */ #define ICE_NVM_AUTH_HEADER_LEN … /* The Link Topology Netlist section is stored as a series of words. It is * stored in the NVM as a TLV, with the first two words containing the type * and length. */ #define ICE_NETLIST_LINK_TOPO_MOD_ID … #define ICE_NETLIST_TYPE_OFFSET … #define ICE_NETLIST_LEN_OFFSET … /* The Link Topology section follows the TLV header. When reading the netlist * using ice_read_netlist_module, we need to account for the 2-word TLV * header. */ #define ICE_NETLIST_LINK_TOPO_OFFSET(n) … #define ICE_LINK_TOPO_MODULE_LEN … #define ICE_LINK_TOPO_NODE_COUNT … #define ICE_LINK_TOPO_NODE_COUNT_M … /* The Netlist ID Block is located after all of the Link Topology nodes. */ #define ICE_NETLIST_ID_BLK_SIZE … #define ICE_NETLIST_ID_BLK_OFFSET(n) … /* netlist ID block field offsets (word offsets) */ #define ICE_NETLIST_ID_BLK_MAJOR_VER_LOW … #define ICE_NETLIST_ID_BLK_MAJOR_VER_HIGH … #define ICE_NETLIST_ID_BLK_MINOR_VER_LOW … #define ICE_NETLIST_ID_BLK_MINOR_VER_HIGH … #define ICE_NETLIST_ID_BLK_TYPE_LOW … #define ICE_NETLIST_ID_BLK_TYPE_HIGH … #define ICE_NETLIST_ID_BLK_REV_LOW … #define ICE_NETLIST_ID_BLK_REV_HIGH … #define ICE_NETLIST_ID_BLK_SHA_HASH_WORD(n) … #define ICE_NETLIST_ID_BLK_CUST_VER … /* Auxiliary field, mask, and shift definition for Shadow RAM and NVM Flash */ #define ICE_SR_CTRL_WORD_1_S … #define ICE_SR_CTRL_WORD_1_M … #define ICE_SR_CTRL_WORD_VALID … #define ICE_SR_CTRL_WORD_OROM_BANK … #define ICE_SR_CTRL_WORD_NETLIST_BANK … #define ICE_SR_CTRL_WORD_NVM_BANK … #define ICE_SR_NVM_PTR_4KB_UNITS … /* Link override related */ #define ICE_SR_PFA_LINK_OVERRIDE_WORDS … #define ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS … #define ICE_SR_PFA_LINK_OVERRIDE_OFFSET … #define ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET … #define ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET … #define ICE_FW_API_LINK_OVERRIDE_MAJ … #define ICE_FW_API_LINK_OVERRIDE_MIN … #define ICE_FW_API_LINK_OVERRIDE_PATCH … #define ICE_SR_WORDS_IN_1KB … /* AQ API version for LLDP_FILTER_CONTROL */ #define ICE_FW_API_LLDP_FLTR_MAJ … #define ICE_FW_API_LLDP_FLTR_MIN … #define ICE_FW_API_LLDP_FLTR_PATCH … /* AQ API version for report default configuration */ #define ICE_FW_API_REPORT_DFLT_CFG_MAJ … #define ICE_FW_API_REPORT_DFLT_CFG_MIN … #define ICE_FW_API_REPORT_DFLT_CFG_PATCH … #endif /* _ICE_TYPE_H_ */
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