/* SPDX-License-Identifier: GPL-2.0 */ /* Copyright (c) 2018, Intel Corporation. */ #ifndef _ICE_SCHED_H_ #define _ICE_SCHED_H_ #include "ice_common.h" /** * DOC: ice_sched.h * * This header file stores everything that is needed for broadly understood * scheduler. It consists of defines related to layers, structures related to * aggregator, functions declarations and others. */ #define ICE_SCHED_5_LAYERS … #define ICE_SCHED_9_LAYERS … #define SCHED_NODE_NAME_MAX_LEN … #define ICE_QGRP_LAYER_OFFSET … #define ICE_VSI_LAYER_OFFSET … #define ICE_AGG_LAYER_OFFSET … #define ICE_SCHED_INVAL_LAYER_NUM … /* Burst size is a 12 bits register that is configured while creating the RL * profile(s). MSB is a granularity bit and tells the granularity type * 0 - LSB bits are in 64 bytes granularity * 1 - LSB bits are in 1K bytes granularity */ #define ICE_64_BYTE_GRANULARITY … #define ICE_KBYTE_GRANULARITY … #define ICE_MIN_BURST_SIZE_ALLOWED … #define ICE_MAX_BURST_SIZE_ALLOWED … #define ICE_MAX_BURST_SIZE_64_BYTE_GRANULARITY … #define ICE_MAX_BURST_SIZE_KBYTE_GRANULARITY … #define ICE_RL_PROF_ACCURACY_BYTES … #define ICE_RL_PROF_MULTIPLIER … #define ICE_RL_PROF_TS_MULTIPLIER … #define ICE_RL_PROF_FRACTION … #define ICE_PSM_CLK_367MHZ_IN_HZ … #define ICE_PSM_CLK_416MHZ_IN_HZ … #define ICE_PSM_CLK_446MHZ_IN_HZ … #define ICE_PSM_CLK_390MHZ_IN_HZ … /* BW rate limit profile parameters list entry along * with bandwidth maintained per layer in port info */ struct ice_aqc_rl_profile_info { … }; struct ice_sched_agg_vsi_info { … }; struct ice_sched_agg_info { … }; /* FW AQ command calls */ int ice_aq_query_sched_elems(struct ice_hw *hw, u16 elems_req, struct ice_aqc_txsched_elem_data *buf, u16 buf_size, u16 *elems_ret, struct ice_sq_cd *cd); int ice_sched_set_node_bw_lmt(struct ice_port_info *pi, struct ice_sched_node *node, enum ice_rl_type rl_type, u32 bw); int ice_sched_set_node_bw(struct ice_port_info *pi, struct ice_sched_node *node, enum ice_rl_type rl_type, u32 bw, u8 layer_num); int ice_sched_add_elems(struct ice_port_info *pi, struct ice_sched_node *tc_node, struct ice_sched_node *parent, u8 layer, u16 num_nodes, u16 *num_nodes_added, u32 *first_node_teid, struct ice_sched_node **prealloc_node); int ice_sched_move_nodes(struct ice_port_info *pi, struct ice_sched_node *parent, u16 num_items, u32 *list); int ice_sched_set_node_priority(struct ice_port_info *pi, struct ice_sched_node *node, u16 priority); int ice_sched_set_node_weight(struct ice_port_info *pi, struct ice_sched_node *node, u16 weight); int ice_sched_init_port(struct ice_port_info *pi); int ice_sched_query_res_alloc(struct ice_hw *hw); void ice_sched_get_psm_clk_freq(struct ice_hw *hw); void ice_sched_clear_port(struct ice_port_info *pi); void ice_sched_cleanup_all(struct ice_hw *hw); void ice_sched_clear_agg(struct ice_hw *hw); struct ice_sched_node * ice_sched_find_node_by_teid(struct ice_sched_node *start_node, u32 teid); int ice_sched_add_node(struct ice_port_info *pi, u8 layer, struct ice_aqc_txsched_elem_data *info, struct ice_sched_node *prealloc_node); void ice_sched_update_parent(struct ice_sched_node *new_parent, struct ice_sched_node *node); void ice_free_sched_node(struct ice_port_info *pi, struct ice_sched_node *node); struct ice_sched_node *ice_sched_get_tc_node(struct ice_port_info *pi, u8 tc); struct ice_sched_node * ice_sched_get_free_qparent(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 owner); int ice_sched_cfg_vsi(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 maxqs, u8 owner, bool enable); int ice_rm_vsi_lan_cfg(struct ice_port_info *pi, u16 vsi_handle); int ice_rm_vsi_rdma_cfg(struct ice_port_info *pi, u16 vsi_handle); /* Tx scheduler rate limiter functions */ int ice_cfg_agg(struct ice_port_info *pi, u32 agg_id, enum ice_agg_type agg_type, u8 tc_bitmap); int ice_move_vsi_to_agg(struct ice_port_info *pi, u32 agg_id, u16 vsi_handle, u8 tc_bitmap); int ice_cfg_q_bw_lmt(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, enum ice_rl_type rl_type, u32 bw); int ice_cfg_q_bw_dflt_lmt(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, enum ice_rl_type rl_type); int ice_cfg_vsi_bw_lmt_per_tc(struct ice_port_info *pi, u16 vsi_handle, u8 tc, enum ice_rl_type rl_type, u32 bw); int ice_cfg_vsi_bw_dflt_lmt_per_tc(struct ice_port_info *pi, u16 vsi_handle, u8 tc, enum ice_rl_type rl_type); int ice_cfg_rl_burst_size(struct ice_hw *hw, u32 bytes); int ice_sched_suspend_resume_elems(struct ice_hw *hw, u8 num_nodes, u32 *node_teids, bool suspend); struct ice_sched_node * ice_sched_get_agg_node(struct ice_port_info *pi, struct ice_sched_node *tc_node, u32 agg_id); u8 ice_sched_get_agg_layer(struct ice_hw *hw); u8 ice_sched_get_vsi_layer(struct ice_hw *hw); struct ice_sched_node * ice_sched_get_free_vsi_parent(struct ice_hw *hw, struct ice_sched_node *node, u16 *num_nodes); int ice_sched_add_nodes_to_layer(struct ice_port_info *pi, struct ice_sched_node *tc_node, struct ice_sched_node *parent, u8 layer, u16 num_nodes, u32 *first_node_teid, u16 *num_nodes_added); void ice_sched_replay_agg_vsi_preinit(struct ice_hw *hw); void ice_sched_replay_agg(struct ice_hw *hw); int ice_aq_move_sched_elems(struct ice_hw *hw, struct ice_aqc_move_elem *buf, u16 buf_size, u16 *grps_movd); int ice_replay_vsi_agg(struct ice_hw *hw, u16 vsi_handle); int ice_sched_replay_q_bw(struct ice_port_info *pi, struct ice_q_ctx *q_ctx); #endif /* _ICE_SCHED_H_ */
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