// SPDX-License-Identifier: GPL-2.0 /* * pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs * * Copyright (C) 2013-2014 Texas Instruments Incorporated - https://www.ti.com * * Authors: Kishon Vijay Abraham I <[email protected]> */ #include <linux/clk.h> #include <linux/delay.h> #include <linux/device.h> #include <linux/err.h> #include <linux/interrupt.h> #include <linux/irq.h> #include <linux/irqchip/chained_irq.h> #include <linux/irqdomain.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/of.h> #include <linux/of_pci.h> #include <linux/pci.h> #include <linux/phy/phy.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/resource.h> #include <linux/types.h> #include <linux/mfd/syscon.h> #include <linux/regmap.h> #include <linux/gpio/consumer.h> #include "../../pci.h" #include "pcie-designware.h" /* PCIe controller wrapper DRA7XX configuration registers */ #define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN … #define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN … #define ERR_SYS … #define ERR_FATAL … #define ERR_NONFATAL … #define ERR_COR … #define ERR_AXI … #define ERR_ECRC … #define PME_TURN_OFF … #define PME_TO_ACK … #define PM_PME … #define LINK_REQ_RST … #define LINK_UP_EVT … #define CFG_BME_EVT … #define CFG_MSE_EVT … #define INTERRUPTS … #define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI … #define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI … #define INTA … #define INTB … #define INTC … #define INTD … #define MSI … #define LEG_EP_INTERRUPTS … #define PCIECTRL_TI_CONF_DEVICE_TYPE … #define DEVICE_TYPE_EP … #define DEVICE_TYPE_LEG_EP … #define DEVICE_TYPE_RC … #define PCIECTRL_DRA7XX_CONF_DEVICE_CMD … #define LTSSM_EN … #define PCIECTRL_DRA7XX_CONF_PHY_CS … #define LINK_UP … #define DRA7XX_CPU_TO_BUS_ADDR … #define PCIECTRL_TI_CONF_INTX_ASSERT … #define PCIECTRL_TI_CONF_INTX_DEASSERT … #define PCIECTRL_TI_CONF_MSI_XMT … #define MSI_REQ_GRANT … #define MSI_VECTOR_SHIFT … #define PCIE_1LANE_2LANE_SELECTION … #define PCIE_B1C0_MODE_SEL … #define PCIE_B0_B1_TSYNCEN … struct dra7xx_pcie { … }; struct dra7xx_pcie_of_data { … }; #define to_dra7xx_pcie(x) … static inline u32 dra7xx_pcie_readl(struct dra7xx_pcie *pcie, u32 offset) { … } static inline void dra7xx_pcie_writel(struct dra7xx_pcie *pcie, u32 offset, u32 value) { … } static u64 dra7xx_pcie_cpu_addr_fixup(struct dw_pcie *pci, u64 cpu_addr) { … } static int dra7xx_pcie_link_up(struct dw_pcie *pci) { … } static void dra7xx_pcie_stop_link(struct dw_pcie *pci) { … } static int dra7xx_pcie_establish_link(struct dw_pcie *pci) { … } static void dra7xx_pcie_enable_msi_interrupts(struct dra7xx_pcie *dra7xx) { … } static void dra7xx_pcie_enable_wrapper_interrupts(struct dra7xx_pcie *dra7xx) { … } static void dra7xx_pcie_enable_interrupts(struct dra7xx_pcie *dra7xx) { … } static int dra7xx_pcie_host_init(struct dw_pcie_rp *pp) { … } static int dra7xx_pcie_intx_map(struct irq_domain *domain, unsigned int irq, irq_hw_number_t hwirq) { … } static const struct irq_domain_ops intx_domain_ops = …; static int dra7xx_pcie_handle_msi(struct dw_pcie_rp *pp, int index) { … } static void dra7xx_pcie_handle_msi_irq(struct dw_pcie_rp *pp) { … } static void dra7xx_pcie_msi_irq_handler(struct irq_desc *desc) { … } static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg) { … } static int dra7xx_pcie_init_irq_domain(struct dw_pcie_rp *pp) { … } static const struct dw_pcie_host_ops dra7xx_pcie_host_ops = …; static void dra7xx_pcie_ep_init(struct dw_pcie_ep *ep) { … } static void dra7xx_pcie_raise_intx_irq(struct dra7xx_pcie *dra7xx) { … } static void dra7xx_pcie_raise_msi_irq(struct dra7xx_pcie *dra7xx, u8 interrupt_num) { … } static int dra7xx_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no, unsigned int type, u16 interrupt_num) { … } static const struct pci_epc_features dra7xx_pcie_epc_features = …; static const struct pci_epc_features* dra7xx_pcie_get_features(struct dw_pcie_ep *ep) { … } static const struct dw_pcie_ep_ops pcie_ep_ops = …; static int dra7xx_add_pcie_ep(struct dra7xx_pcie *dra7xx, struct platform_device *pdev) { … } static int dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx, struct platform_device *pdev) { … } static const struct dw_pcie_ops dw_pcie_ops = …; static void dra7xx_pcie_disable_phy(struct dra7xx_pcie *dra7xx) { … } static int dra7xx_pcie_enable_phy(struct dra7xx_pcie *dra7xx) { … } static const struct dra7xx_pcie_of_data dra7xx_pcie_rc_of_data = …; static const struct dra7xx_pcie_of_data dra7xx_pcie_ep_of_data = …; static const struct dra7xx_pcie_of_data dra746_pcie_rc_of_data = …; static const struct dra7xx_pcie_of_data dra726_pcie_rc_of_data = …; static const struct dra7xx_pcie_of_data dra746_pcie_ep_of_data = …; static const struct dra7xx_pcie_of_data dra726_pcie_ep_of_data = …; static const struct of_device_id of_dra7xx_pcie_match[] = …; MODULE_DEVICE_TABLE(of, of_dra7xx_pcie_match); /* * dra7xx_pcie_unaligned_memaccess: workaround for AM572x/AM571x Errata i870 * @dra7xx: the dra7xx device where the workaround should be applied * * Access to the PCIe slave port that are not 32-bit aligned will result * in incorrect mapping to TLP Address and Byte enable fields. Therefore, * byte and half-word accesses are not possible to byte offset 0x1, 0x2, or * 0x3. * * To avoid this issue set PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE to 1. */ static int dra7xx_pcie_unaligned_memaccess(struct device *dev) { … } static int dra7xx_pcie_configure_two_lane(struct device *dev, u32 b1co_mode_sel_mask) { … } static int dra7xx_pcie_probe(struct platform_device *pdev) { … } static int dra7xx_pcie_suspend(struct device *dev) { … } static int dra7xx_pcie_resume(struct device *dev) { … } static int dra7xx_pcie_suspend_noirq(struct device *dev) { … } static int dra7xx_pcie_resume_noirq(struct device *dev) { … } static void dra7xx_pcie_shutdown(struct platform_device *pdev) { … } static const struct dev_pm_ops dra7xx_pcie_pm_ops = …; static struct platform_driver dra7xx_pcie_driver = …; module_platform_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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