/* SPDX-License-Identifier: GPL-2.0-only */ /* Copyright (C) 2023 Intel Corporation */ #ifndef _IDPF_LAN_TXRX_H_ #define _IDPF_LAN_TXRX_H_ #include <linux/bits.h> enum idpf_rss_hash { … }; /* Supported RSS offloads */ #define IDPF_DEFAULT_RSS_HASH … #define IDPF_DEFAULT_RSS_HASH_EXPANDED … /* For idpf_splitq_base_tx_compl_desc */ #define IDPF_TXD_COMPLQ_GEN_S … #define IDPF_TXD_COMPLQ_GEN_M … #define IDPF_TXD_COMPLQ_COMPL_TYPE_S … #define IDPF_TXD_COMPLQ_COMPL_TYPE_M … #define IDPF_TXD_COMPLQ_QID_S … #define IDPF_TXD_COMPLQ_QID_M … /* For base mode TX descriptors */ #define IDPF_TXD_CTX_QW0_TUNN_L4T_CS_S … #define IDPF_TXD_CTX_QW0_TUNN_L4T_CS_M … #define IDPF_TXD_CTX_QW0_TUNN_DECTTL_S … #define IDPF_TXD_CTX_QW0_TUNN_DECTTL_M … #define IDPF_TXD_CTX_QW0_TUNN_NATLEN_S … #define IDPF_TXD_CTX_QW0_TUNN_NATLEN_M … #define IDPF_TXD_CTX_QW0_TUNN_EIP_NOINC_S … #define IDPF_TXD_CTX_QW0_TUNN_EIP_NOINC_M … #define IDPF_TXD_CTX_EIP_NOINC_IPID_CONST … #define IDPF_TXD_CTX_QW0_TUNN_NATT_S … #define IDPF_TXD_CTX_QW0_TUNN_NATT_M … #define IDPF_TXD_CTX_UDP_TUNNELING … #define IDPF_TXD_CTX_GRE_TUNNELING … #define IDPF_TXD_CTX_QW0_TUNN_EXT_IPLEN_S … #define IDPF_TXD_CTX_QW0_TUNN_EXT_IPLEN_M … #define IDPF_TXD_CTX_QW0_TUNN_EXT_IP_S … #define IDPF_TXD_CTX_QW0_TUNN_EXT_IP_M … #define IDPF_TXD_CTX_QW1_MSS_S … #define IDPF_TXD_CTX_QW1_MSS_M … #define IDPF_TXD_CTX_QW1_TSO_LEN_S … #define IDPF_TXD_CTX_QW1_TSO_LEN_M … #define IDPF_TXD_CTX_QW1_CMD_S … #define IDPF_TXD_CTX_QW1_CMD_M … #define IDPF_TXD_CTX_QW1_DTYPE_S … #define IDPF_TXD_CTX_QW1_DTYPE_M … #define IDPF_TXD_QW1_L2TAG1_S … #define IDPF_TXD_QW1_L2TAG1_M … #define IDPF_TXD_QW1_TX_BUF_SZ_S … #define IDPF_TXD_QW1_TX_BUF_SZ_M … #define IDPF_TXD_QW1_OFFSET_S … #define IDPF_TXD_QW1_OFFSET_M … #define IDPF_TXD_QW1_CMD_S … #define IDPF_TXD_QW1_CMD_M … #define IDPF_TXD_QW1_DTYPE_S … #define IDPF_TXD_QW1_DTYPE_M … /* TX Completion Descriptor Completion Types */ #define IDPF_TXD_COMPLT_ITR_FLUSH … /* Descriptor completion type 1 is reserved */ #define IDPF_TXD_COMPLT_RS … /* Descriptor completion type 3 is reserved */ #define IDPF_TXD_COMPLT_RE … #define IDPF_TXD_COMPLT_SW_MARKER … enum idpf_tx_desc_dtype_value { … }; enum idpf_tx_ctx_desc_cmd_bits { … }; enum idpf_tx_desc_len_fields { … }; enum idpf_tx_base_desc_cmd_bits { … }; /* Transmit descriptors */ /* splitq tx buf, singleq tx buf and singleq compl desc */ struct idpf_base_tx_desc { … }; /* read used with buffer queues */ struct idpf_splitq_tx_compl_desc { … }; /* writeback used with completion queues */ /* Context descriptors */ struct idpf_base_tx_ctx_desc { … }; /* Common cmd field defines for all desc except Flex Flow Scheduler (0x0C) */ enum idpf_tx_flex_desc_cmd_bits { … }; struct idpf_flex_tx_desc { … }; struct idpf_flex_tx_sched_desc { … }; /* Common cmd fields for all flex context descriptors * Note: these defines already account for the 5 bit dtype in the cmd_dtype * field */ enum idpf_tx_flex_ctx_desc_cmd_bits { … }; /* Standard flex descriptor TSO context quad word */ struct idpf_flex_tx_tso_ctx_qw { … }; struct idpf_flex_tx_ctx_desc { … }; #endif /* _IDPF_LAN_TXRX_H_ */
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