/* SPDX-License-Identifier: GPL-2.0-only */ /* Copyright (C) 2023 Intel Corporation */ #ifndef _IDPF_LAN_VF_REGS_H_ #define _IDPF_LAN_VF_REGS_H_ /* Reset */ #define VFGEN_RSTAT … #define VFGEN_RSTAT_VFR_STATE_S … #define VFGEN_RSTAT_VFR_STATE_M … /* Control(VF Mailbox) Queue */ #define VF_BASE … #define VF_ATQBAL … #define VF_ATQBAH … #define VF_ATQLEN … #define VF_ATQLEN_ATQLEN_S … #define VF_ATQLEN_ATQLEN_M … #define VF_ATQLEN_ATQVFE_S … #define VF_ATQLEN_ATQVFE_M … #define VF_ATQLEN_ATQOVFL_S … #define VF_ATQLEN_ATQOVFL_M … #define VF_ATQLEN_ATQCRIT_S … #define VF_ATQLEN_ATQCRIT_M … #define VF_ATQLEN_ATQENABLE_S … #define VF_ATQLEN_ATQENABLE_M … #define VF_ATQH … #define VF_ATQH_ATQH_S … #define VF_ATQH_ATQH_M … #define VF_ATQT … #define VF_ARQBAL … #define VF_ARQBAH … #define VF_ARQLEN … #define VF_ARQLEN_ARQLEN_S … #define VF_ARQLEN_ARQLEN_M … #define VF_ARQLEN_ARQVFE_S … #define VF_ARQLEN_ARQVFE_M … #define VF_ARQLEN_ARQOVFL_S … #define VF_ARQLEN_ARQOVFL_M … #define VF_ARQLEN_ARQCRIT_S … #define VF_ARQLEN_ARQCRIT_M … #define VF_ARQLEN_ARQENABLE_S … #define VF_ARQLEN_ARQENABLE_M … #define VF_ARQH … #define VF_ARQH_ARQH_S … #define VF_ARQH_ARQH_M … #define VF_ARQT … /* Transmit queues */ #define VF_QTX_TAIL_BASE … #define VF_QTX_TAIL(_QTX) … #define VF_QTX_TAIL_EXT_BASE … #define VF_QTX_TAIL_EXT(_QTX) … /* Receive queues */ #define VF_QRX_TAIL_BASE … #define VF_QRX_TAIL(_QRX) … #define VF_QRX_TAIL_EXT_BASE … #define VF_QRX_TAIL_EXT(_QRX) … #define VF_QRXB_TAIL_BASE … #define VF_QRXB_TAIL(_QRX) … /* Interrupts */ #define VF_INT_DYN_CTL0 … #define VF_INT_DYN_CTL0_INTENA_S … #define VF_INT_DYN_CTL0_INTENA_M … #define VF_INT_DYN_CTL0_ITR_INDX_S … #define VF_INT_DYN_CTL0_ITR_INDX_M … #define VF_INT_DYN_CTLN(_INT) … #define VF_INT_DYN_CTLN_EXT(_INT) … #define VF_INT_DYN_CTLN_INTENA_S … #define VF_INT_DYN_CTLN_INTENA_M … #define VF_INT_DYN_CTLN_CLEARPBA_S … #define VF_INT_DYN_CTLN_CLEARPBA_M … #define VF_INT_DYN_CTLN_SWINT_TRIG_S … #define VF_INT_DYN_CTLN_SWINT_TRIG_M … #define VF_INT_DYN_CTLN_ITR_INDX_S … #define VF_INT_DYN_CTLN_ITR_INDX_M … #define VF_INT_DYN_CTLN_INTERVAL_S … #define VF_INT_DYN_CTLN_INTERVAL_M … #define VF_INT_DYN_CTLN_SW_ITR_INDX_ENA_S … #define VF_INT_DYN_CTLN_SW_ITR_INDX_ENA_M … #define VF_INT_DYN_CTLN_SW_ITR_INDX_S … #define VF_INT_DYN_CTLN_SW_ITR_INDX_M … #define VF_INT_DYN_CTLN_WB_ON_ITR_S … #define VF_INT_DYN_CTLN_WB_ON_ITR_M … #define VF_INT_DYN_CTLN_INTENA_MSK_S … #define VF_INT_DYN_CTLN_INTENA_MSK_M … /* _ITR is ITR index, _INT is interrupt index, _itrn_indx_spacing is spacing * b/w itrn registers of the same vector */ #define VF_INT_ITR0(_ITR) … #define VF_INT_ITRN_ADDR(_ITR, _reg_start, _itrn_indx_spacing) … /* For VF with 16 vector support, itrn_reg_spacing is 0x4, itrn_indx_spacing * is 0x40 and base register offset is 0x00002800 */ #define VF_INT_ITRN(_INT, _ITR) … /* For VF with 64 vector support, itrn_reg_spacing is 0x4, itrn_indx_spacing * is 0x100 and base register offset is 0x00002C00 */ #define VF_INT_ITRN_64(_INT, _ITR) … /* For VF with 2k vector support, itrn_reg_spacing is 0x4, itrn_indx_spacing * is 0x2000 and base register offset is 0x00072000 */ #define VF_INT_ITRN_2K(_INT, _ITR) … #define VF_INT_ITRN_MAX_INDEX … #define VF_INT_ITRN_INTERVAL_S … #define VF_INT_ITRN_INTERVAL_M … #define VF_INT_PBA_CLEAR … #define VF_INT_ICR0_ENA1 … #define VF_INT_ICR0_ENA1_ADMINQ_S … #define VF_INT_ICR0_ENA1_ADMINQ_M … #define VF_INT_ICR0_ENA1_RSVD_S … #define VF_INT_ICR01 … #define VF_QF_HENA(_i) … #define VF_QF_HENA_MAX_INDX … #define VF_QF_HKEY(_i) … #define VF_QF_HKEY_MAX_INDX … #define VF_QF_HLUT(_i) … #define VF_QF_HLUT_MAX_INDX … #endif
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