// SPDX-License-Identifier: GPL-2.0 /* * PCIe host controller driver for Texas Instruments Keystone SoCs * * Copyright (C) 2013-2014 Texas Instruments., Ltd. * https://www.ti.com * * Author: Murali Karicheri <[email protected]> * Implementation based on pci-exynos.c and pcie-designware.c */ #include <linux/clk.h> #include <linux/delay.h> #include <linux/gpio/consumer.h> #include <linux/init.h> #include <linux/interrupt.h> #include <linux/irqchip/chained_irq.h> #include <linux/irqdomain.h> #include <linux/mfd/syscon.h> #include <linux/msi.h> #include <linux/of.h> #include <linux/of_irq.h> #include <linux/of_pci.h> #include <linux/phy/phy.h> #include <linux/platform_device.h> #include <linux/regmap.h> #include <linux/resource.h> #include <linux/signal.h> #include "../../pci.h" #include "pcie-designware.h" #define PCIE_VENDORID_MASK … #define PCIE_DEVICEID_SHIFT … /* Application registers */ #define PID … #define RTL … #define RTL_SHIFT … #define AM6_PCI_PG1_RTL_VER … #define CMD_STATUS … #define LTSSM_EN_VAL … #define OB_XLAT_EN_VAL … #define DBI_CS2 … #define CFG_SETUP … #define CFG_BUS(x) … #define CFG_DEVICE(x) … #define CFG_FUNC(x) … #define CFG_TYPE1 … #define OB_SIZE … #define OB_OFFSET_INDEX(n) … #define OB_OFFSET_HI(n) … #define OB_ENABLEN … #define OB_WIN_SIZE … #define PCIE_LEGACY_IRQ_ENABLE_SET(n) … #define PCIE_LEGACY_IRQ_ENABLE_CLR(n) … #define PCIE_EP_IRQ_SET … #define PCIE_EP_IRQ_CLR … #define INT_ENABLE … /* IRQ register defines */ #define IRQ_EOI … #define MSI_IRQ … #define MSI_IRQ_STATUS(n) … #define MSI_IRQ_ENABLE_SET(n) … #define MSI_IRQ_ENABLE_CLR(n) … #define MSI_IRQ_OFFSET … #define IRQ_STATUS(n) … #define IRQ_ENABLE_SET(n) … #define INTx_EN … #define ERR_IRQ_STATUS … #define ERR_IRQ_ENABLE_SET … #define ERR_AER … #define AM6_ERR_AER … #define ERR_AXI … #define ERR_CORR … #define ERR_NONFATAL … #define ERR_FATAL … #define ERR_SYS … #define ERR_IRQ_ALL … /* PCIE controller device IDs */ #define PCIE_RC_K2HK … #define PCIE_RC_K2E … #define PCIE_RC_K2L … #define PCIE_RC_K2G … #define KS_PCIE_DEV_TYPE_MASK … #define KS_PCIE_DEV_TYPE(mode) … #define EP … #define LEG_EP … #define RC … #define KS_PCIE_SYSCLOCKOUTEN … #define AM654_PCIE_DEV_TYPE_MASK … #define AM654_WIN_SIZE … #define APP_ADDR_SPACE_0 … #define to_keystone_pcie(x) … #define PCI_DEVICE_ID_TI_AM654X … struct ks_pcie_of_data { … }; struct keystone_pcie { … }; static u32 ks_pcie_app_readl(struct keystone_pcie *ks_pcie, u32 offset) { … } static void ks_pcie_app_writel(struct keystone_pcie *ks_pcie, u32 offset, u32 val) { … } static void ks_pcie_msi_irq_ack(struct irq_data *data) { … } static void ks_pcie_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) { … } static void ks_pcie_msi_mask(struct irq_data *data) { … } static void ks_pcie_msi_unmask(struct irq_data *data) { … } static struct irq_chip ks_pcie_msi_irq_chip = …; /** * ks_pcie_set_dbi_mode() - Set DBI mode to access overlaid BAR mask registers * @ks_pcie: A pointer to the keystone_pcie structure which holds the KeyStone * PCIe host controller driver information. * * Since modification of dbi_cs2 involves different clock domain, read the * status back to ensure the transition is complete. */ static void ks_pcie_set_dbi_mode(struct keystone_pcie *ks_pcie) { … } /** * ks_pcie_clear_dbi_mode() - Disable DBI mode * @ks_pcie: A pointer to the keystone_pcie structure which holds the KeyStone * PCIe host controller driver information. * * Since modification of dbi_cs2 involves different clock domain, read the * status back to ensure the transition is complete. */ static void ks_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie) { … } static int ks_pcie_msi_host_init(struct dw_pcie_rp *pp) { … } static void ks_pcie_handle_intx_irq(struct keystone_pcie *ks_pcie, int offset) { … } static void ks_pcie_enable_error_irq(struct keystone_pcie *ks_pcie) { … } static irqreturn_t ks_pcie_handle_error_irq(struct keystone_pcie *ks_pcie) { … } static void ks_pcie_ack_intx_irq(struct irq_data *d) { … } static void ks_pcie_mask_intx_irq(struct irq_data *d) { … } static void ks_pcie_unmask_intx_irq(struct irq_data *d) { … } static struct irq_chip ks_pcie_intx_irq_chip = …; static int ks_pcie_init_intx_irq_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw_irq) { … } static const struct irq_domain_ops ks_pcie_intx_irq_domain_ops = …; static int ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie) { … } static void __iomem *ks_pcie_other_map_bus(struct pci_bus *bus, unsigned int devfn, int where) { … } static struct pci_ops ks_child_pcie_ops = …; static struct pci_ops ks_pcie_ops = …; /** * ks_pcie_link_up() - Check if link up * @pci: A pointer to the dw_pcie structure which holds the DesignWare PCIe host * controller driver information. */ static int ks_pcie_link_up(struct dw_pcie *pci) { … } static void ks_pcie_stop_link(struct dw_pcie *pci) { … } static int ks_pcie_start_link(struct dw_pcie *pci) { … } static void ks_pcie_quirk(struct pci_dev *dev) { … } DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, ks_pcie_quirk); static void ks_pcie_msi_irq_handler(struct irq_desc *desc) { … } /** * ks_pcie_intx_irq_handler() - Handle INTX interrupt * @desc: Pointer to irq descriptor * * Traverse through pending INTX interrupts and invoke handler for each. Also * takes care of interrupt controller level mask/ack operation. */ static void ks_pcie_intx_irq_handler(struct irq_desc *desc) { … } static int ks_pcie_config_msi_irq(struct keystone_pcie *ks_pcie) { … } static int ks_pcie_config_intx_irq(struct keystone_pcie *ks_pcie) { … } #ifdef CONFIG_ARM /* * When a PCI device does not exist during config cycles, keystone host * gets a bus error instead of returning 0xffffffff (PCI_ERROR_RESPONSE). * This handler always returns 0 for this kind of fault. */ static int ks_pcie_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs) { unsigned long instr = *(unsigned long *) instruction_pointer(regs); if ((instr & 0x0e100090) == 0x00100090) { int reg = (instr >> 12) & 15; regs->uregs[reg] = -1; regs->ARM_pc += 4; } return 0; } #endif static int __init ks_pcie_init_id(struct keystone_pcie *ks_pcie) { … } static int __init ks_pcie_host_init(struct dw_pcie_rp *pp) { … } static const struct dw_pcie_host_ops ks_pcie_host_ops = …; static const struct dw_pcie_host_ops ks_pcie_am654_host_ops = …; static irqreturn_t ks_pcie_err_irq_handler(int irq, void *priv) { … } static void ks_pcie_am654_write_dbi2(struct dw_pcie *pci, void __iomem *base, u32 reg, size_t size, u32 val) { … } static const struct dw_pcie_ops ks_pcie_dw_pcie_ops = …; static void ks_pcie_am654_ep_init(struct dw_pcie_ep *ep) { … } static void ks_pcie_am654_raise_intx_irq(struct keystone_pcie *ks_pcie) { … } static int ks_pcie_am654_raise_irq(struct dw_pcie_ep *ep, u8 func_no, unsigned int type, u16 interrupt_num) { … } static const struct pci_epc_features ks_pcie_am654_epc_features = …; static const struct pci_epc_features* ks_pcie_am654_get_features(struct dw_pcie_ep *ep) { … } static const struct dw_pcie_ep_ops ks_pcie_am654_ep_ops = …; static void ks_pcie_disable_phy(struct keystone_pcie *ks_pcie) { … } static int ks_pcie_enable_phy(struct keystone_pcie *ks_pcie) { … } static int ks_pcie_set_mode(struct device *dev) { … } static int ks_pcie_am654_set_mode(struct device *dev, enum dw_pcie_device_mode mode) { … } static const struct ks_pcie_of_data ks_pcie_rc_of_data = …; static const struct ks_pcie_of_data ks_pcie_am654_rc_of_data = …; static const struct ks_pcie_of_data ks_pcie_am654_ep_of_data = …; static const struct of_device_id ks_pcie_of_match[] = …; static int ks_pcie_probe(struct platform_device *pdev) { … } static void ks_pcie_remove(struct platform_device *pdev) { … } static struct platform_driver ks_pcie_driver = …; builtin_platform_driver(…) …;
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