// SPDX-License-Identifier: GPL-2.0 /* * Qualcomm PCIe Endpoint controller driver * * Copyright (c) 2020, The Linux Foundation. All rights reserved. * Author: Siddartha Mohanadoss <[email protected] * * Copyright (c) 2021, Linaro Ltd. * Author: Manivannan Sadhasivam <[email protected] */ #include <linux/clk.h> #include <linux/debugfs.h> #include <linux/delay.h> #include <linux/gpio/consumer.h> #include <linux/interconnect.h> #include <linux/mfd/syscon.h> #include <linux/phy/pcie.h> #include <linux/phy/phy.h> #include <linux/platform_device.h> #include <linux/pm_domain.h> #include <linux/regmap.h> #include <linux/reset.h> #include <linux/module.h> #include "../../pci.h" #include "pcie-designware.h" #include "pcie-qcom-common.h" /* PARF registers */ #define PARF_SYS_CTRL … #define PARF_DB_CTRL … #define PARF_PM_CTRL … #define PARF_MHI_CLOCK_RESET_CTRL … #define PARF_MHI_BASE_ADDR_LOWER … #define PARF_MHI_BASE_ADDR_UPPER … #define PARF_DEBUG_INT_EN … #define PARF_AXI_MSTR_RD_HALT_NO_WRITES … #define PARF_AXI_MSTR_WR_ADDR_HALT … #define PARF_Q2A_FLUSH … #define PARF_LTSSM … #define PARF_CFG_BITS … #define PARF_INT_ALL_STATUS … #define PARF_INT_ALL_CLEAR … #define PARF_INT_ALL_MASK … #define PARF_SLV_ADDR_MSB_CTRL … #define PARF_DBI_BASE_ADDR … #define PARF_DBI_BASE_ADDR_HI … #define PARF_SLV_ADDR_SPACE_SIZE … #define PARF_SLV_ADDR_SPACE_SIZE_HI … #define PARF_NO_SNOOP_OVERIDE … #define PARF_ATU_BASE_ADDR … #define PARF_ATU_BASE_ADDR_HI … #define PARF_SRIS_MODE … #define PARF_DEBUG_CNT_PM_LINKST_IN_L2 … #define PARF_DEBUG_CNT_PM_LINKST_IN_L1 … #define PARF_DEBUG_CNT_PM_LINKST_IN_L0S … #define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1 … #define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2 … #define PARF_DEVICE_TYPE … #define PARF_BDF_TO_SID_CFG … #define PARF_INT_ALL_5_MASK … /* PARF_INT_ALL_{STATUS/CLEAR/MASK} register fields */ #define PARF_INT_ALL_LINK_DOWN … #define PARF_INT_ALL_BME … #define PARF_INT_ALL_PM_TURNOFF … #define PARF_INT_ALL_DEBUG … #define PARF_INT_ALL_LTR … #define PARF_INT_ALL_MHI_Q6 … #define PARF_INT_ALL_MHI_A7 … #define PARF_INT_ALL_DSTATE_CHANGE … #define PARF_INT_ALL_L1SUB_TIMEOUT … #define PARF_INT_ALL_MMIO_WRITE … #define PARF_INT_ALL_CFG_WRITE … #define PARF_INT_ALL_BRIDGE_FLUSH_N … #define PARF_INT_ALL_LINK_UP … #define PARF_INT_ALL_AER_LEGACY … #define PARF_INT_ALL_PLS_ERR … #define PARF_INT_ALL_PME_LEGACY … #define PARF_INT_ALL_PLS_PME … #define PARF_INT_ALL_EDMA … /* PARF_BDF_TO_SID_CFG register fields */ #define PARF_BDF_TO_SID_BYPASS … /* PARF_DEBUG_INT_EN register fields */ #define PARF_DEBUG_INT_PM_DSTATE_CHANGE … #define PARF_DEBUG_INT_CFG_BUS_MASTER_EN … #define PARF_DEBUG_INT_RADM_PM_TURNOFF … /* PARF_NO_SNOOP_OVERIDE register fields */ #define WR_NO_SNOOP_OVERIDE_EN … #define RD_NO_SNOOP_OVERIDE_EN … /* PARF_DEVICE_TYPE register fields */ #define PARF_DEVICE_TYPE_EP … /* PARF_PM_CTRL register fields */ #define PARF_PM_CTRL_REQ_EXIT_L1 … #define PARF_PM_CTRL_READY_ENTR_L23 … #define PARF_PM_CTRL_REQ_NOT_ENTR_L1 … /* PARF_MHI_CLOCK_RESET_CTRL fields */ #define PARF_MSTR_AXI_CLK_EN … /* PARF_AXI_MSTR_RD_HALT_NO_WRITES register fields */ #define PARF_AXI_MSTR_RD_HALT_NO_WRITE_EN … /* PARF_AXI_MSTR_WR_ADDR_HALT register fields */ #define PARF_AXI_MSTR_WR_ADDR_HALT_EN … /* PARF_Q2A_FLUSH register fields */ #define PARF_Q2A_FLUSH_EN … /* PARF_SYS_CTRL register fields */ #define PARF_SYS_CTRL_AUX_PWR_DET … #define PARF_SYS_CTRL_CORE_CLK_CGC_DIS … #define PARF_SYS_CTRL_MSTR_ACLK_CGC_DIS … #define PARF_SYS_CTRL_SLV_DBI_WAKE_DISABLE … /* PARF_DB_CTRL register fields */ #define PARF_DB_CTRL_INSR_DBNCR_BLOCK … #define PARF_DB_CTRL_RMVL_DBNCR_BLOCK … #define PARF_DB_CTRL_DBI_WKP_BLOCK … #define PARF_DB_CTRL_SLV_WKP_BLOCK … #define PARF_DB_CTRL_MST_WKP_BLOCK … /* PARF_CFG_BITS register fields */ #define PARF_CFG_BITS_REQ_EXIT_L1SS_MSI_LTR_EN … /* PARF_INT_ALL_5_MASK fields */ #define PARF_INT_ALL_5_MHI_RAM_DATA_PARITY_ERR … /* ELBI registers */ #define ELBI_SYS_STTS … #define ELBI_CS2_ENABLE … /* DBI registers */ #define DBI_CON_STATUS … /* DBI register fields */ #define DBI_CON_STATUS_POWER_STATE_MASK … #define XMLH_LINK_UP … #define CORE_RESET_TIME_US_MIN … #define CORE_RESET_TIME_US_MAX … #define WAKE_DELAY_US … #define QCOM_PCIE_LINK_SPEED_TO_BW(speed) … #define to_pcie_ep(x) … enum qcom_pcie_ep_link_status { … }; /** * struct qcom_pcie_ep_cfg - Per SoC config struct * @hdma_support: HDMA support on this SoC * @override_no_snoop: Override NO_SNOOP attribute in TLP to enable cache snooping * @disable_mhi_ram_parity_check: Disable MHI RAM data parity error check */ struct qcom_pcie_ep_cfg { … }; /** * struct qcom_pcie_ep - Qualcomm PCIe Endpoint Controller * @pci: Designware PCIe controller struct * @parf: Qualcomm PCIe specific PARF register base * @elbi: Designware PCIe specific ELBI register base * @mmio: MMIO register base * @perst_map: PERST regmap * @mmio_res: MMIO region resource * @core_reset: PCIe Endpoint core reset * @reset: PERST# GPIO * @wake: WAKE# GPIO * @phy: PHY controller block * @debugfs: PCIe Endpoint Debugfs directory * @icc_mem: Handle to an interconnect path between PCIe and MEM * @clks: PCIe clocks * @num_clks: PCIe clocks count * @perst_en: Flag for PERST enable * @perst_sep_en: Flag for PERST separation enable * @cfg: PCIe EP config struct * @link_status: PCIe Link status * @global_irq: Qualcomm PCIe specific Global IRQ * @perst_irq: PERST# IRQ */ struct qcom_pcie_ep { … }; static int qcom_pcie_ep_core_reset(struct qcom_pcie_ep *pcie_ep) { … } /* * Delatch PERST_EN and PERST_SEPARATION_ENABLE with TCSR to avoid * device reset during host reboot and hibernation. The driver is * expected to handle this situation. */ static void qcom_pcie_ep_configure_tcsr(struct qcom_pcie_ep *pcie_ep) { … } static int qcom_pcie_dw_link_up(struct dw_pcie *pci) { … } static int qcom_pcie_dw_start_link(struct dw_pcie *pci) { … } static void qcom_pcie_dw_stop_link(struct dw_pcie *pci) { … } static void qcom_pcie_dw_write_dbi2(struct dw_pcie *pci, void __iomem *base, u32 reg, size_t size, u32 val) { … } static void qcom_pcie_ep_icc_update(struct qcom_pcie_ep *pcie_ep) { … } static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep) { … } static void qcom_pcie_disable_resources(struct qcom_pcie_ep *pcie_ep) { … } static int qcom_pcie_perst_deassert(struct dw_pcie *pci) { … } static void qcom_pcie_perst_assert(struct dw_pcie *pci) { … } /* Common DWC controller ops */ static const struct dw_pcie_ops pci_ops = …; static int qcom_pcie_ep_get_io_resources(struct platform_device *pdev, struct qcom_pcie_ep *pcie_ep) { … } static int qcom_pcie_ep_get_resources(struct platform_device *pdev, struct qcom_pcie_ep *pcie_ep) { … } /* TODO: Notify clients about PCIe state change */ static irqreturn_t qcom_pcie_ep_global_irq_thread(int irq, void *data) { … } static irqreturn_t qcom_pcie_ep_perst_irq_thread(int irq, void *data) { … } static int qcom_pcie_ep_enable_irq_resources(struct platform_device *pdev, struct qcom_pcie_ep *pcie_ep) { … } static int qcom_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, unsigned int type, u16 interrupt_num) { … } static int qcom_pcie_ep_link_transition_count(struct seq_file *s, void *data) { … } static void qcom_pcie_ep_init_debugfs(struct qcom_pcie_ep *pcie_ep) { … } static const struct pci_epc_features qcom_pcie_epc_features = …; static const struct pci_epc_features * qcom_pcie_epc_get_features(struct dw_pcie_ep *pci_ep) { … } static void qcom_pcie_ep_init(struct dw_pcie_ep *ep) { … } static const struct dw_pcie_ep_ops pci_ep_ops = …; static int qcom_pcie_ep_probe(struct platform_device *pdev) { … } static void qcom_pcie_ep_remove(struct platform_device *pdev) { … } static const struct qcom_pcie_ep_cfg cfg_1_34_0 = …; static const struct of_device_id qcom_pcie_ep_match[] = …; MODULE_DEVICE_TABLE(of, qcom_pcie_ep_match); static struct platform_driver qcom_pcie_ep_driver = …; builtin_platform_driver(…) …; MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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