// SPDX-License-Identifier: GPL-2.0 /* * PCIe host controller driver for Kirin Phone SoCs * * Copyright (C) 2017 HiSilicon Electronics Co., Ltd. * https://www.huawei.com * * Author: Xiaowei Song <[email protected]> */ #include <linux/clk.h> #include <linux/compiler.h> #include <linux/delay.h> #include <linux/err.h> #include <linux/gpio/consumer.h> #include <linux/interrupt.h> #include <linux/mfd/syscon.h> #include <linux/of.h> #include <linux/of_pci.h> #include <linux/phy/phy.h> #include <linux/pci.h> #include <linux/pci_regs.h> #include <linux/platform_device.h> #include <linux/regmap.h> #include <linux/resource.h> #include <linux/types.h> #include "pcie-designware.h" #define to_kirin_pcie(x) … /* PCIe ELBI registers */ #define SOC_PCIECTRL_CTRL0_ADDR … #define SOC_PCIECTRL_CTRL1_ADDR … #define PCIE_ELBI_SLV_DBI_ENABLE … /* info located in APB */ #define PCIE_APP_LTSSM_ENABLE … #define PCIE_APB_PHY_STATUS0 … #define PCIE_LINKUP_ENABLE … #define PCIE_LTSSM_ENABLE_BIT … /* info located in sysctrl */ #define SCTRL_PCIE_CMOS_OFFSET … #define SCTRL_PCIE_CMOS_BIT … #define SCTRL_PCIE_ISO_OFFSET … #define SCTRL_PCIE_ISO_BIT … #define SCTRL_PCIE_HPCLK_OFFSET … #define SCTRL_PCIE_HPCLK_BIT … #define SCTRL_PCIE_OE_OFFSET … #define PCIE_DEBOUNCE_PARAM … #define PCIE_OE_BYPASS … /* * Max number of connected PCI slots at an external PCI bridge * * This is used on HiKey 970, which has a PEX 8606 bridge with 4 connected * lanes (lane 0 upstream, and the other three lanes, one connected to an * in-board Ethernet adapter and the other two connected to M.2 and mini * PCI slots. * * Each slot has a different clock source and uses a separate PERST# pin. */ #define MAX_PCI_SLOTS … enum pcie_kirin_phy_type { … }; struct kirin_pcie { … }; /* * Kirin 960 PHY. Can't be split into a PHY driver without changing the * DT schema. */ #define REF_CLK_FREQ … /* PHY info located in APB */ #define PCIE_APB_PHY_CTRL0 … #define PCIE_APB_PHY_CTRL1 … #define PCIE_APB_PHY_STATUS0 … #define PIPE_CLK_STABLE … #define PHY_REF_PAD_BIT … #define PHY_PWR_DOWN_BIT … #define PHY_RST_ACK_BIT … /* peri_crg ctrl */ #define CRGCTRL_PCIE_ASSERT_OFFSET … #define CRGCTRL_PCIE_ASSERT_BIT … /* Time for delay */ #define REF_2_PERST_MIN … #define REF_2_PERST_MAX … #define PERST_2_ACCESS_MIN … #define PERST_2_ACCESS_MAX … #define PIPE_CLK_WAIT_MIN … #define PIPE_CLK_WAIT_MAX … #define TIME_CMOS_MIN … #define TIME_CMOS_MAX … #define TIME_PHY_PD_MIN … #define TIME_PHY_PD_MAX … struct hi3660_pcie_phy { … }; /* Registers in PCIePHY */ static inline void kirin_apb_phy_writel(struct hi3660_pcie_phy *hi3660_pcie_phy, u32 val, u32 reg) { … } static inline u32 kirin_apb_phy_readl(struct hi3660_pcie_phy *hi3660_pcie_phy, u32 reg) { … } static int hi3660_pcie_phy_get_clk(struct hi3660_pcie_phy *phy) { … } static int hi3660_pcie_phy_get_resource(struct hi3660_pcie_phy *phy) { … } static int hi3660_pcie_phy_start(struct hi3660_pcie_phy *phy) { … } static void hi3660_pcie_phy_oe_enable(struct hi3660_pcie_phy *phy) { … } static int hi3660_pcie_phy_clk_ctrl(struct hi3660_pcie_phy *phy, bool enable) { … } static int hi3660_pcie_phy_power_on(struct kirin_pcie *pcie) { … } static int hi3660_pcie_phy_init(struct platform_device *pdev, struct kirin_pcie *pcie) { … } static int hi3660_pcie_phy_power_off(struct kirin_pcie *pcie) { … } /* * The non-PHY part starts here */ static const struct regmap_config pcie_kirin_regmap_conf = …; static int kirin_pcie_get_gpio_enable(struct kirin_pcie *pcie, struct platform_device *pdev) { … } static int kirin_pcie_parse_port(struct kirin_pcie *pcie, struct platform_device *pdev, struct device_node *node) { … } static long kirin_pcie_get_resource(struct kirin_pcie *kirin_pcie, struct platform_device *pdev) { … } static void kirin_pcie_sideband_dbi_w_mode(struct kirin_pcie *kirin_pcie, bool on) { … } static void kirin_pcie_sideband_dbi_r_mode(struct kirin_pcie *kirin_pcie, bool on) { … } static int kirin_pcie_rd_own_conf(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val) { … } static int kirin_pcie_wr_own_conf(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val) { … } static int kirin_pcie_add_bus(struct pci_bus *bus) { … } static struct pci_ops kirin_pci_ops = …; static u32 kirin_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg, size_t size) { … } static void kirin_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg, size_t size, u32 val) { … } static int kirin_pcie_link_up(struct dw_pcie *pci) { … } static int kirin_pcie_start_link(struct dw_pcie *pci) { … } static int kirin_pcie_host_init(struct dw_pcie_rp *pp) { … } static const struct dw_pcie_ops kirin_dw_pcie_ops = …; static const struct dw_pcie_host_ops kirin_pcie_host_ops = …; static int kirin_pcie_power_off(struct kirin_pcie *kirin_pcie) { … } static int kirin_pcie_power_on(struct platform_device *pdev, struct kirin_pcie *kirin_pcie) { … } static void kirin_pcie_remove(struct platform_device *pdev) { … } struct kirin_pcie_data { … }; static const struct kirin_pcie_data kirin_960_data = …; static const struct kirin_pcie_data kirin_970_data = …; static const struct of_device_id kirin_pcie_match[] = …; static int kirin_pcie_probe(struct platform_device *pdev) { … } static struct platform_driver kirin_pcie_driver = …; module_platform_driver(…) …; MODULE_DEVICE_TABLE(of, kirin_pcie_match); MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …;
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