// SPDX-License-Identifier: GPL-2.0 /* * Support for Faraday Technology FTPC100 PCI Controller * * Copyright (C) 2017 Linus Walleij <[email protected]> * * Based on the out-of-tree OpenWRT patch for Cortina Gemini: * Copyright (C) 2009 Janos Laube <[email protected]> * Copyright (C) 2009 Paulius Zaleckas <[email protected]> * Based on SL2312 PCI controller code * Storlink (C) 2003 */ #include <linux/init.h> #include <linux/interrupt.h> #include <linux/io.h> #include <linux/kernel.h> #include <linux/of.h> #include <linux/of_irq.h> #include <linux/of_pci.h> #include <linux/pci.h> #include <linux/platform_device.h> #include <linux/slab.h> #include <linux/irqdomain.h> #include <linux/irqchip/chained_irq.h> #include <linux/bitops.h> #include <linux/irq.h> #include <linux/clk.h> #include "../pci.h" /* * Special configuration registers directly in the first few words * in I/O space. */ #define FTPCI_IOSIZE … #define FTPCI_PROT … #define FTPCI_CTRL … #define FTPCI_SOFTRST … #define FTPCI_CONFIG … #define FTPCI_DATA … #define FARADAY_PCI_STATUS_CMD … #define FARADAY_PCI_PMC … #define FARADAY_PCI_PMCSR … #define FARADAY_PCI_CTRL1 … #define FARADAY_PCI_CTRL2 … #define FARADAY_PCI_MEM1_BASE_SIZE … #define FARADAY_PCI_MEM2_BASE_SIZE … #define FARADAY_PCI_MEM3_BASE_SIZE … #define PCI_STATUS_66MHZ_CAPABLE … /* Bits 31..28 gives INTD..INTA status */ #define PCI_CTRL2_INTSTS_SHIFT … #define PCI_CTRL2_INTMASK_CMDERR … #define PCI_CTRL2_INTMASK_PARERR … /* Bits 25..22 masks INTD..INTA */ #define PCI_CTRL2_INTMASK_SHIFT … #define PCI_CTRL2_INTMASK_MABRT_RX … #define PCI_CTRL2_INTMASK_TABRT_RX … #define PCI_CTRL2_INTMASK_TABRT_TX … #define PCI_CTRL2_INTMASK_RETRY4 … #define PCI_CTRL2_INTMASK_SERR_RX … #define PCI_CTRL2_INTMASK_PERR_RX … /* Bit 15 reserved */ #define PCI_CTRL2_MSTPRI_REQ6 … #define PCI_CTRL2_MSTPRI_REQ5 … #define PCI_CTRL2_MSTPRI_REQ4 … #define PCI_CTRL2_MSTPRI_REQ3 … #define PCI_CTRL2_MSTPRI_REQ2 … #define PCI_CTRL2_MSTPRI_REQ1 … #define PCI_CTRL2_MSTPRI_REQ0 … /* Bits 7..4 reserved */ /* Bits 3..0 TRDYW */ /* * Memory configs: * Bit 31..20 defines the PCI side memory base * Bit 19..16 (4 bits) defines the size per below */ #define FARADAY_PCI_MEMBASE_MASK … #define FARADAY_PCI_MEMSIZE_1MB … #define FARADAY_PCI_MEMSIZE_2MB … #define FARADAY_PCI_MEMSIZE_4MB … #define FARADAY_PCI_MEMSIZE_8MB … #define FARADAY_PCI_MEMSIZE_16MB … #define FARADAY_PCI_MEMSIZE_32MB … #define FARADAY_PCI_MEMSIZE_64MB … #define FARADAY_PCI_MEMSIZE_128MB … #define FARADAY_PCI_MEMSIZE_256MB … #define FARADAY_PCI_MEMSIZE_512MB … #define FARADAY_PCI_MEMSIZE_1GB … #define FARADAY_PCI_MEMSIZE_2GB … #define FARADAY_PCI_MEMSIZE_SHIFT … /* * The DMA base is set to 0x0 for all memory segments, it reflects the * fact that the memory of the host system starts at 0x0. */ #define FARADAY_PCI_DMA_MEM1_BASE … #define FARADAY_PCI_DMA_MEM2_BASE … #define FARADAY_PCI_DMA_MEM3_BASE … /** * struct faraday_pci_variant - encodes IP block differences * @cascaded_irq: this host has cascaded IRQs from an interrupt controller * embedded in the host bridge. */ struct faraday_pci_variant { … }; struct faraday_pci { … }; static int faraday_res_to_memcfg(resource_size_t mem_base, resource_size_t mem_size, u32 *val) { … } static int faraday_raw_pci_read_config(struct faraday_pci *p, int bus_number, unsigned int fn, int config, int size, u32 *value) { … } static int faraday_pci_read_config(struct pci_bus *bus, unsigned int fn, int config, int size, u32 *value) { … } static int faraday_raw_pci_write_config(struct faraday_pci *p, int bus_number, unsigned int fn, int config, int size, u32 value) { … } static int faraday_pci_write_config(struct pci_bus *bus, unsigned int fn, int config, int size, u32 value) { … } static struct pci_ops faraday_pci_ops = …; static void faraday_pci_ack_irq(struct irq_data *d) { … } static void faraday_pci_mask_irq(struct irq_data *d) { … } static void faraday_pci_unmask_irq(struct irq_data *d) { … } static void faraday_pci_irq_handler(struct irq_desc *desc) { … } static struct irq_chip faraday_pci_irq_chip = …; static int faraday_pci_irq_map(struct irq_domain *domain, unsigned int irq, irq_hw_number_t hwirq) { … } static const struct irq_domain_ops faraday_pci_irqdomain_ops = …; static int faraday_pci_setup_cascaded_irq(struct faraday_pci *p) { … } static int faraday_pci_parse_map_dma_ranges(struct faraday_pci *p) { … } static int faraday_pci_probe(struct platform_device *pdev) { … } /* * We encode bridge variants here, we have at least two so it doesn't * hurt to have infrastructure to encompass future variants as well. */ static const struct faraday_pci_variant faraday_regular = …; static const struct faraday_pci_variant faraday_dual = …; static const struct of_device_id faraday_pci_of_match[] = …; static struct platform_driver faraday_pci_driver = …; builtin_platform_driver(…) …;
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