// SPDX-License-Identifier: GPL-2.0 /* * Copyright Altera Corporation (C) 2013-2015. All rights reserved * * Author: Ley Foon Tan <[email protected]> * Description: Altera PCIe host controller driver */ #include <linux/delay.h> #include <linux/interrupt.h> #include <linux/irqchip/chained_irq.h> #include <linux/irqdomain.h> #include <linux/init.h> #include <linux/module.h> #include <linux/of.h> #include <linux/of_pci.h> #include <linux/pci.h> #include <linux/platform_device.h> #include <linux/slab.h> #include "../pci.h" #define RP_TX_REG0 … #define RP_TX_REG1 … #define RP_TX_CNTRL … #define RP_TX_EOP … #define RP_TX_SOP … #define RP_RXCPL_STATUS … #define RP_RXCPL_EOP … #define RP_RXCPL_SOP … #define RP_RXCPL_REG0 … #define RP_RXCPL_REG1 … #define P2A_INT_STATUS … #define P2A_INT_STS_ALL … #define P2A_INT_ENABLE … #define P2A_INT_ENA_ALL … #define RP_LTSSM … #define RP_LTSSM_MASK … #define LTSSM_L0 … #define S10_RP_TX_CNTRL … #define S10_RP_RXCPL_REG … #define S10_RP_RXCPL_STATUS … #define S10_RP_CFG_ADDR(pcie, reg) … #define S10_RP_SECONDARY(pcie) … /* TLP configuration type 0 and 1 */ #define TLP_FMTTYPE_CFGRD0 … #define TLP_FMTTYPE_CFGWR0 … #define TLP_FMTTYPE_CFGRD1 … #define TLP_FMTTYPE_CFGWR1 … #define TLP_PAYLOAD_SIZE … #define TLP_READ_TAG … #define TLP_WRITE_TAG … #define RP_DEVFN … #define TLP_CFG_DW0(pcie, cfg) … #define TLP_CFG_DW1(pcie, tag, be) … #define TLP_CFG_DW2(bus, devfn, offset) … #define TLP_COMP_STATUS(s) … #define TLP_BYTE_COUNT(s) … #define TLP_HDR_SIZE … #define TLP_LOOP … #define LINK_UP_TIMEOUT … #define LINK_RETRAIN_TIMEOUT … #define DWORD_MASK … #define S10_TLP_FMTTYPE_CFGRD0 … #define S10_TLP_FMTTYPE_CFGRD1 … #define S10_TLP_FMTTYPE_CFGWR0 … #define S10_TLP_FMTTYPE_CFGWR1 … enum altera_pcie_version { … }; struct altera_pcie { … }; struct altera_pcie_ops { … }; struct altera_pcie_data { … }; struct tlp_rp_regpair_t { … }; static inline void cra_writel(struct altera_pcie *pcie, const u32 value, const u32 reg) { … } static inline u32 cra_readl(struct altera_pcie *pcie, const u32 reg) { … } static bool altera_pcie_link_up(struct altera_pcie *pcie) { … } static bool s10_altera_pcie_link_up(struct altera_pcie *pcie) { … } /* * Altera PCIe port uses BAR0 of RC's configuration space as the translation * from PCI bus to native BUS. Entire DDR region is mapped into PCIe space * using these registers, so it can be reached by DMA from EP devices. * This BAR0 will also access to MSI vector when receiving MSI/MSIX interrupt * from EP devices, eventually trigger interrupt to GIC. The BAR0 of bridge * should be hidden during enumeration to avoid the sizing and resource * allocation by PCIe core. */ static bool altera_pcie_hide_rc_bar(struct pci_bus *bus, unsigned int devfn, int offset) { … } static void tlp_write_tx(struct altera_pcie *pcie, struct tlp_rp_regpair_t *tlp_rp_regdata) { … } static void s10_tlp_write_tx(struct altera_pcie *pcie, u32 reg0, u32 ctrl) { … } static bool altera_pcie_valid_device(struct altera_pcie *pcie, struct pci_bus *bus, int dev) { … } static int tlp_read_packet(struct altera_pcie *pcie, u32 *value) { … } static int s10_tlp_read_packet(struct altera_pcie *pcie, u32 *value) { … } static void tlp_write_packet(struct altera_pcie *pcie, u32 *headers, u32 data, bool align) { … } static void s10_tlp_write_packet(struct altera_pcie *pcie, u32 *headers, u32 data, bool dummy) { … } static void get_tlp_header(struct altera_pcie *pcie, u8 bus, u32 devfn, int where, u8 byte_en, bool read, u32 *headers) { … } static int tlp_cfg_dword_read(struct altera_pcie *pcie, u8 bus, u32 devfn, int where, u8 byte_en, u32 *value) { … } static int tlp_cfg_dword_write(struct altera_pcie *pcie, u8 bus, u32 devfn, int where, u8 byte_en, u32 value) { … } static int s10_rp_read_cfg(struct altera_pcie *pcie, int where, int size, u32 *value) { … } static int s10_rp_write_cfg(struct altera_pcie *pcie, u8 busno, int where, int size, u32 value) { … } static int _altera_pcie_cfg_read(struct altera_pcie *pcie, u8 busno, unsigned int devfn, int where, int size, u32 *value) { … } static int _altera_pcie_cfg_write(struct altera_pcie *pcie, u8 busno, unsigned int devfn, int where, int size, u32 value) { … } static int altera_pcie_cfg_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value) { … } static int altera_pcie_cfg_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value) { … } static struct pci_ops altera_pcie_ops = …; static int altera_read_cap_word(struct altera_pcie *pcie, u8 busno, unsigned int devfn, int offset, u16 *value) { … } static int altera_write_cap_word(struct altera_pcie *pcie, u8 busno, unsigned int devfn, int offset, u16 value) { … } static void altera_wait_link_retrain(struct altera_pcie *pcie) { … } static void altera_pcie_retrain(struct altera_pcie *pcie) { … } static int altera_pcie_intx_map(struct irq_domain *domain, unsigned int irq, irq_hw_number_t hwirq) { … } static const struct irq_domain_ops intx_domain_ops = …; static void altera_pcie_isr(struct irq_desc *desc) { … } static int altera_pcie_init_irq_domain(struct altera_pcie *pcie) { … } static void altera_pcie_irq_teardown(struct altera_pcie *pcie) { … } static int altera_pcie_parse_dt(struct altera_pcie *pcie) { … } static void altera_pcie_host_init(struct altera_pcie *pcie) { … } static const struct altera_pcie_ops altera_pcie_ops_1_0 = …; static const struct altera_pcie_ops altera_pcie_ops_2_0 = …; static const struct altera_pcie_data altera_pcie_1_0_data = …; static const struct altera_pcie_data altera_pcie_2_0_data = …; static const struct of_device_id altera_pcie_of_match[] = …; static int altera_pcie_probe(struct platform_device *pdev) { … } static void altera_pcie_remove(struct platform_device *pdev) { … } static struct platform_driver altera_pcie_driver = …; MODULE_DEVICE_TABLE(of, altera_pcie_of_match); module_platform_driver(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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