// SPDX-License-Identifier: GPL-2.0 /* * MediaTek PCIe host controller driver. * * Copyright (c) 2017 MediaTek Inc. * Author: Ryder Lee <[email protected]> * Honghui Zhang <[email protected]> */ #include <linux/clk.h> #include <linux/delay.h> #include <linux/iopoll.h> #include <linux/irq.h> #include <linux/irqchip/chained_irq.h> #include <linux/irqdomain.h> #include <linux/kernel.h> #include <linux/mfd/syscon.h> #include <linux/msi.h> #include <linux/module.h> #include <linux/of_address.h> #include <linux/of_pci.h> #include <linux/of_platform.h> #include <linux/pci.h> #include <linux/phy/phy.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/regmap.h> #include <linux/reset.h> #include "../pci.h" /* PCIe shared registers */ #define PCIE_SYS_CFG … #define PCIE_INT_ENABLE … #define PCIE_CFG_ADDR … #define PCIE_CFG_DATA … /* PCIe per port registers */ #define PCIE_BAR0_SETUP … #define PCIE_CLASS … #define PCIE_LINK_STATUS … #define PCIE_PORT_INT_EN(x) … #define PCIE_PORT_PERST(x) … #define PCIE_PORT_LINKUP … #define PCIE_BAR_MAP_MAX … #define PCIE_BAR_ENABLE … #define PCIE_REVISION_ID … #define PCIE_CLASS_CODE … #define PCIE_CONF_REG(regn) … #define PCIE_CONF_FUN(fun) … #define PCIE_CONF_DEV(dev) … #define PCIE_CONF_BUS(bus) … #define PCIE_CONF_ADDR(regn, fun, dev, bus) … /* MediaTek specific configuration registers */ #define PCIE_FTS_NUM … #define PCIE_FTS_NUM_MASK … #define PCIE_FTS_NUM_L0(x) … #define PCIE_FC_CREDIT … #define PCIE_FC_CREDIT_MASK … #define PCIE_FC_CREDIT_VAL(x) … /* PCIe V2 share registers */ #define PCIE_SYS_CFG_V2 … #define PCIE_CSR_LTSSM_EN(x) … #define PCIE_CSR_ASPM_L1_EN(x) … /* PCIe V2 per-port registers */ #define PCIE_MSI_VECTOR … #define PCIE_CONF_VEND_ID … #define PCIE_CONF_DEVICE_ID … #define PCIE_CONF_CLASS_ID … #define PCIE_INT_MASK … #define INTX_MASK … #define INTX_SHIFT … #define PCIE_INT_STATUS … #define MSI_STATUS … #define PCIE_IMSI_STATUS … #define PCIE_IMSI_ADDR … #define MSI_MASK … #define MTK_MSI_IRQS_NUM … #define PCIE_AHB_TRANS_BASE0_L … #define PCIE_AHB_TRANS_BASE0_H … #define AHB2PCIE_SIZE(x) … #define PCIE_AXI_WINDOW0 … #define WIN_ENABLE … /* * Define PCIe to AHB window size as 2^33 to support max 8GB address space * translate, support least 4GB DRAM size access from EP DMA(physical DRAM * start from 0x40000000). */ #define PCIE2AHB_SIZE … /* PCIe V2 configuration transaction header */ #define PCIE_CFG_HEADER0 … #define PCIE_CFG_HEADER1 … #define PCIE_CFG_HEADER2 … #define PCIE_CFG_WDATA … #define PCIE_APP_TLP_REQ … #define PCIE_CFG_RDATA … #define APP_CFG_REQ … #define APP_CPL_STATUS … #define CFG_WRRD_TYPE_0 … #define CFG_WR_FMT … #define CFG_RD_FMT … #define CFG_DW0_LENGTH(length) … #define CFG_DW0_TYPE(type) … #define CFG_DW0_FMT(fmt) … #define CFG_DW2_REGN(regn) … #define CFG_DW2_FUN(fun) … #define CFG_DW2_DEV(dev) … #define CFG_DW2_BUS(bus) … #define CFG_HEADER_DW0(type, fmt) … #define CFG_HEADER_DW1(where, size) … #define CFG_HEADER_DW2(regn, fun, dev, bus) … #define PCIE_RST_CTRL … #define PCIE_PHY_RSTB … #define PCIE_PIPE_SRSTB … #define PCIE_MAC_SRSTB … #define PCIE_CRSTB … #define PCIE_PERSTB … #define PCIE_LINKDOWN_RST_EN … #define PCIE_LINK_STATUS_V2 … #define PCIE_PORT_LINKUP_V2 … struct mtk_pcie_port; /** * struct mtk_pcie_soc - differentiate between host generations * @need_fix_class_id: whether this host's class ID needed to be fixed or not * @need_fix_device_id: whether this host's device ID needed to be fixed or not * @no_msi: Bridge has no MSI support, and relies on an external block * @device_id: device ID which this host need to be fixed * @ops: pointer to configuration access functions * @startup: pointer to controller setting functions * @setup_irq: pointer to initialize IRQ functions */ struct mtk_pcie_soc { … }; /** * struct mtk_pcie_port - PCIe port information * @base: IO mapped register base * @list: port list * @pcie: pointer to PCIe host info * @reset: pointer to port reset control * @sys_ck: pointer to transaction/data link layer clock * @ahb_ck: pointer to AHB slave interface operating clock for CSR access * and RC initiated MMIO access * @axi_ck: pointer to application layer MMIO channel operating clock * @aux_ck: pointer to pe2_mac_bridge and pe2_mac_core operating clock * when pcie_mac_ck/pcie_pipe_ck is turned off * @obff_ck: pointer to OBFF functional block operating clock * @pipe_ck: pointer to LTSSM and PHY/MAC layer operating clock * @phy: pointer to PHY control block * @slot: port slot * @irq: GIC irq * @irq_domain: legacy INTx IRQ domain * @inner_domain: inner IRQ domain * @msi_domain: MSI IRQ domain * @lock: protect the msi_irq_in_use bitmap * @msi_irq_in_use: bit map for assigned MSI IRQ */ struct mtk_pcie_port { … }; /** * struct mtk_pcie - PCIe host information * @dev: pointer to PCIe device * @base: IO mapped register base * @cfg: IO mapped register map for PCIe config * @free_ck: free-run reference clock * @ports: pointer to PCIe port information * @soc: pointer to SoC-dependent operations */ struct mtk_pcie { … }; static void mtk_pcie_subsys_powerdown(struct mtk_pcie *pcie) { … } static void mtk_pcie_port_free(struct mtk_pcie_port *port) { … } static void mtk_pcie_put_resources(struct mtk_pcie *pcie) { … } static int mtk_pcie_check_cfg_cpld(struct mtk_pcie_port *port) { … } static int mtk_pcie_hw_rd_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn, int where, int size, u32 *val) { … } static int mtk_pcie_hw_wr_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn, int where, int size, u32 val) { … } static struct mtk_pcie_port *mtk_pcie_find_port(struct pci_bus *bus, unsigned int devfn) { … } static int mtk_pcie_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val) { … } static int mtk_pcie_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val) { … } static struct pci_ops mtk_pcie_ops_v2 = …; static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) { … } static void mtk_msi_ack_irq(struct irq_data *data) { … } static struct irq_chip mtk_msi_bottom_irq_chip = …; static int mtk_pcie_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs, void *args) { … } static void mtk_pcie_irq_domain_free(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs) { … } static const struct irq_domain_ops msi_domain_ops = …; static struct irq_chip mtk_msi_irq_chip = …; static struct msi_domain_info mtk_msi_domain_info = …; static int mtk_pcie_allocate_msi_domains(struct mtk_pcie_port *port) { … } static void mtk_pcie_enable_msi(struct mtk_pcie_port *port) { … } static void mtk_pcie_irq_teardown(struct mtk_pcie *pcie) { … } static int mtk_pcie_intx_map(struct irq_domain *domain, unsigned int irq, irq_hw_number_t hwirq) { … } static const struct irq_domain_ops intx_domain_ops = …; static int mtk_pcie_init_irq_domain(struct mtk_pcie_port *port, struct device_node *node) { … } static void mtk_pcie_intr_handler(struct irq_desc *desc) { … } static int mtk_pcie_setup_irq(struct mtk_pcie_port *port, struct device_node *node) { … } static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) { … } static void __iomem *mtk_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, int where) { … } static struct pci_ops mtk_pcie_ops = …; static int mtk_pcie_startup_port(struct mtk_pcie_port *port) { … } static void mtk_pcie_enable_port(struct mtk_pcie_port *port) { … } static int mtk_pcie_parse_port(struct mtk_pcie *pcie, struct device_node *node, int slot) { … } static int mtk_pcie_subsys_powerup(struct mtk_pcie *pcie) { … } static int mtk_pcie_setup(struct mtk_pcie *pcie) { … } static int mtk_pcie_probe(struct platform_device *pdev) { … } static void mtk_pcie_free_resources(struct mtk_pcie *pcie) { … } static void mtk_pcie_remove(struct platform_device *pdev) { … } static int mtk_pcie_suspend_noirq(struct device *dev) { … } static int mtk_pcie_resume_noirq(struct device *dev) { … } static const struct dev_pm_ops mtk_pcie_pm_ops = …; static const struct mtk_pcie_soc mtk_pcie_soc_v1 = …; static const struct mtk_pcie_soc mtk_pcie_soc_mt2712 = …; static const struct mtk_pcie_soc mtk_pcie_soc_mt7622 = …; static const struct mtk_pcie_soc mtk_pcie_soc_mt7629 = …; static const struct of_device_id mtk_pcie_ids[] = …; MODULE_DEVICE_TABLE(of, mtk_pcie_ids); static struct platform_driver mtk_pcie_driver = …; module_platform_driver(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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