/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 1999 - 2010 Intel Corporation. * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD. * * This code was derived from the Intel e1000e Linux driver. */ #ifndef _PCH_GBE_H_ #define _PCH_GBE_H_ #define pr_fmt(fmt) … #include <linux/mii.h> #include <linux/delay.h> #include <linux/pci.h> #include <linux/netdevice.h> #include <linux/etherdevice.h> #include <linux/ethtool.h> #include <linux/vmalloc.h> #include <net/ip.h> #include <net/tcp.h> #include <net/udp.h> /** * pch_gbe_regs_mac_adr - Structure holding values of mac address registers * @high Denotes the 1st to 4th byte from the initial of MAC address * @low Denotes the 5th to 6th byte from the initial of MAC address */ struct pch_gbe_regs_mac_adr { … }; /** * pch_udc_regs - Structure holding values of MAC registers */ struct pch_gbe_regs { … }; /* Interrupt Status */ /* Interrupt Status Hold */ /* Interrupt Enable */ #define PCH_GBE_INT_RX_DMA_CMPLT … #define PCH_GBE_INT_RX_VALID … #define PCH_GBE_INT_RX_FRAME_ERR … #define PCH_GBE_INT_RX_FIFO_ERR … #define PCH_GBE_INT_RX_DMA_ERR … #define PCH_GBE_INT_RX_DSC_EMP … #define PCH_GBE_INT_TX_CMPLT … #define PCH_GBE_INT_TX_DMA_CMPLT … #define PCH_GBE_INT_TX_FIFO_ERR … #define PCH_GBE_INT_TX_DMA_ERR … #define PCH_GBE_INT_PAUSE_CMPLT … #define PCH_GBE_INT_MIIM_CMPLT … #define PCH_GBE_INT_PHY_INT … #define PCH_GBE_INT_WOL_DET … #define PCH_GBE_INT_TCPIP_ERR … /* Mode */ #define PCH_GBE_MODE_MII_ETHER … #define PCH_GBE_MODE_GMII_ETHER … #define PCH_GBE_MODE_HALF_DUPLEX … #define PCH_GBE_MODE_FULL_DUPLEX … #define PCH_GBE_MODE_FR_BST … /* Reset */ #define PCH_GBE_ALL_RST … #define PCH_GBE_TX_RST … #define PCH_GBE_RX_RST … /* TCP/IP Accelerator Control */ #define PCH_GBE_EX_LIST_EN … #define PCH_GBE_RX_TCPIPACC_OFF … #define PCH_GBE_TX_TCPIPACC_EN … #define PCH_GBE_RX_TCPIPACC_EN … /* MAC RX Enable */ #define PCH_GBE_MRE_MAC_RX_EN … /* RX Flow Control */ #define PCH_GBE_FL_CTRL_EN … /* Pause Packet Request */ #define PCH_GBE_PS_PKT_RQ … /* RX Mode */ #define PCH_GBE_ADD_FIL_EN … /* Multicast Filtering Enable */ #define PCH_GBE_MLT_FIL_EN … /* Receive Almost Empty Threshold */ #define PCH_GBE_RH_ALM_EMP_4 … #define PCH_GBE_RH_ALM_EMP_8 … #define PCH_GBE_RH_ALM_EMP_16 … #define PCH_GBE_RH_ALM_EMP_32 … /* Receive Almost Full Threshold */ #define PCH_GBE_RH_ALM_FULL_4 … #define PCH_GBE_RH_ALM_FULL_8 … #define PCH_GBE_RH_ALM_FULL_16 … #define PCH_GBE_RH_ALM_FULL_32 … /* RX FIFO Read Trigger Threshold */ #define PCH_GBE_RH_RD_TRG_4 … #define PCH_GBE_RH_RD_TRG_8 … #define PCH_GBE_RH_RD_TRG_16 … #define PCH_GBE_RH_RD_TRG_32 … #define PCH_GBE_RH_RD_TRG_64 … #define PCH_GBE_RH_RD_TRG_128 … #define PCH_GBE_RH_RD_TRG_256 … #define PCH_GBE_RH_RD_TRG_512 … /* Receive Descriptor bit definitions */ #define PCH_GBE_RXD_ACC_STAT_BCAST … #define PCH_GBE_RXD_ACC_STAT_MCAST … #define PCH_GBE_RXD_ACC_STAT_UCAST … #define PCH_GBE_RXD_ACC_STAT_TCPIPOK … #define PCH_GBE_RXD_ACC_STAT_IPOK … #define PCH_GBE_RXD_ACC_STAT_TCPOK … #define PCH_GBE_RXD_ACC_STAT_IP6ERR … #define PCH_GBE_RXD_ACC_STAT_OFLIST … #define PCH_GBE_RXD_ACC_STAT_TYPEIP … #define PCH_GBE_RXD_ACC_STAT_MACL … #define PCH_GBE_RXD_ACC_STAT_PPPOE … #define PCH_GBE_RXD_ACC_STAT_VTAGT … #define PCH_GBE_RXD_GMAC_STAT_PAUSE … #define PCH_GBE_RXD_GMAC_STAT_MARBR … #define PCH_GBE_RXD_GMAC_STAT_MARMLT … #define PCH_GBE_RXD_GMAC_STAT_MARIND … #define PCH_GBE_RXD_GMAC_STAT_MARNOTMT … #define PCH_GBE_RXD_GMAC_STAT_TLONG … #define PCH_GBE_RXD_GMAC_STAT_TSHRT … #define PCH_GBE_RXD_GMAC_STAT_NOTOCTAL … #define PCH_GBE_RXD_GMAC_STAT_NBLERR … #define PCH_GBE_RXD_GMAC_STAT_CRCERR … /* Transmit Descriptor bit definitions */ #define PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF … #define PCH_GBE_TXD_CTRL_ITAG … #define PCH_GBE_TXD_CTRL_ICRC … #define PCH_GBE_TXD_CTRL_APAD … #define PCH_GBE_TXD_WORDS_SHIFT … #define PCH_GBE_TXD_GMAC_STAT_CMPLT … #define PCH_GBE_TXD_GMAC_STAT_ABT … #define PCH_GBE_TXD_GMAC_STAT_EXCOL … #define PCH_GBE_TXD_GMAC_STAT_SNGCOL … #define PCH_GBE_TXD_GMAC_STAT_MLTCOL … #define PCH_GBE_TXD_GMAC_STAT_CRSER … #define PCH_GBE_TXD_GMAC_STAT_TLNG … #define PCH_GBE_TXD_GMAC_STAT_TSHRT … #define PCH_GBE_TXD_GMAC_STAT_LTCOL … #define PCH_GBE_TXD_GMAC_STAT_TFUNDFLW … #define PCH_GBE_TXD_GMAC_STAT_RTYCNT_MASK … /* TX Mode */ #define PCH_GBE_TM_NO_RTRY … #define PCH_GBE_TM_LONG_PKT … #define PCH_GBE_TM_ST_AND_FD … #define PCH_GBE_TM_SHORT_PKT … #define PCH_GBE_TM_LTCOL_RETX … /* Frame Start Threshold */ #define PCH_GBE_TM_TH_TX_STRT_4 … #define PCH_GBE_TM_TH_TX_STRT_8 … #define PCH_GBE_TM_TH_TX_STRT_16 … #define PCH_GBE_TM_TH_TX_STRT_32 … /* Transmit Almost Empty Threshold */ #define PCH_GBE_TM_TH_ALM_EMP_4 … #define PCH_GBE_TM_TH_ALM_EMP_8 … #define PCH_GBE_TM_TH_ALM_EMP_16 … #define PCH_GBE_TM_TH_ALM_EMP_32 … #define PCH_GBE_TM_TH_ALM_EMP_64 … #define PCH_GBE_TM_TH_ALM_EMP_128 … #define PCH_GBE_TM_TH_ALM_EMP_256 … #define PCH_GBE_TM_TH_ALM_EMP_512 … /* Transmit Almost Full Threshold */ #define PCH_GBE_TM_TH_ALM_FULL_4 … #define PCH_GBE_TM_TH_ALM_FULL_8 … #define PCH_GBE_TM_TH_ALM_FULL_16 … #define PCH_GBE_TM_TH_ALM_FULL_32 … /* RX FIFO Status */ #define PCH_GBE_RF_ALM_FULL … #define PCH_GBE_RF_ALM_EMP … #define PCH_GBE_RF_RD_TRG … #define PCH_GBE_RF_STRWD … #define PCH_GBE_RF_RCVING … /* MAC Address Mask */ #define PCH_GBE_BUSY … /* MIIM */ #define PCH_GBE_MIIM_OPER_WRITE … #define PCH_GBE_MIIM_OPER_READ … #define PCH_GBE_MIIM_OPER_READY … #define PCH_GBE_MIIM_PHY_ADDR_SHIFT … #define PCH_GBE_MIIM_REG_ADDR_SHIFT … /* RGMII Status */ #define PCH_GBE_LINK_UP … #define PCH_GBE_RXC_SPEED_MSK … #define PCH_GBE_RXC_SPEED_2_5M … #define PCH_GBE_RXC_SPEED_25M … #define PCH_GBE_RXC_SPEED_125M … #define PCH_GBE_DUPLEX_FULL … /* RGMII Control */ #define PCH_GBE_CRS_SEL … #define PCH_GBE_RGMII_RATE_125M … #define PCH_GBE_RGMII_RATE_25M … #define PCH_GBE_RGMII_RATE_2_5M … #define PCH_GBE_RGMII_MODE_GMII … #define PCH_GBE_RGMII_MODE_RGMII … #define PCH_GBE_CHIP_TYPE_EXTERNAL … #define PCH_GBE_CHIP_TYPE_INTERNAL … /* DMA Control */ #define PCH_GBE_RX_DMA_EN … #define PCH_GBE_TX_DMA_EN … /* RX DMA STATUS */ #define PCH_GBE_IDLE_CHECK … /* Wake On LAN Status */ #define PCH_GBE_WLS_BR … #define PCH_GBE_WLS_MLT … /* The Frame registered in Address Recognizer */ #define PCH_GBE_WLS_IND … #define PCH_GBE_WLS_MP … /* Wake On LAN Control */ #define PCH_GBE_WLC_WOL_MODE … #define PCH_GBE_WLC_IGN_TLONG … #define PCH_GBE_WLC_IGN_TSHRT … #define PCH_GBE_WLC_IGN_OCTER … #define PCH_GBE_WLC_IGN_NBLER … #define PCH_GBE_WLC_IGN_CRCER … #define PCH_GBE_WLC_BR … #define PCH_GBE_WLC_MLT … #define PCH_GBE_WLC_IND … #define PCH_GBE_WLC_MP … /* Wake On LAN Address Mask */ #define PCH_GBE_WLA_BUSY … /* TX/RX descriptor defines */ #define PCH_GBE_MAX_TXD … #define PCH_GBE_DEFAULT_TXD … #define PCH_GBE_MIN_TXD … #define PCH_GBE_MAX_RXD … #define PCH_GBE_DEFAULT_RXD … #define PCH_GBE_MIN_RXD … /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ #define PCH_GBE_TX_DESC_MULTIPLE … #define PCH_GBE_RX_DESC_MULTIPLE … /* Read/Write operation is done through MII Management IF */ #define PCH_GBE_HAL_MIIM_READ … #define PCH_GBE_HAL_MIIM_WRITE … /* flow control values */ #define PCH_GBE_FC_NONE … #define PCH_GBE_FC_RX_PAUSE … #define PCH_GBE_FC_TX_PAUSE … #define PCH_GBE_FC_FULL … #define PCH_GBE_FC_DEFAULT … /** * struct pch_gbe_mac_info - MAC information * @addr[6]: Store the MAC address * @fc: Mode of flow control * @fc_autoneg: Auto negotiation enable for flow control setting * @tx_fc_enable: Enable flag of Transmit flow control * @max_frame_size: Max transmit frame size * @min_frame_size: Min transmit frame size * @autoneg: Auto negotiation enable * @link_speed: Link speed * @link_duplex: Link duplex */ struct pch_gbe_mac_info { … }; /** * struct pch_gbe_phy_info - PHY information * @addr: PHY address * @id: PHY's identifier * @revision: PHY's revision * @reset_delay_us: HW reset delay time[us] * @autoneg_advertised: Autoneg advertised */ struct pch_gbe_phy_info { … }; /*! * @ingroup Gigabit Ether driver Layer * @struct pch_gbe_hw * @brief Hardware information */ struct pch_gbe_hw { … }; /** * struct pch_gbe_rx_desc - Receive Descriptor * @buffer_addr: RX Frame Buffer Address * @tcp_ip_status: TCP/IP Accelerator Status * @rx_words_eob: RX word count and Byte position * @gbec_status: GMAC Status * @dma_status: DMA Status * @reserved1: Reserved * @reserved2: Reserved */ struct pch_gbe_rx_desc { … }; /** * struct pch_gbe_tx_desc - Transmit Descriptor * @buffer_addr: TX Frame Buffer Address * @length: Data buffer length * @reserved1: Reserved * @tx_words_eob: TX word count and Byte position * @tx_frame_ctrl: TX Frame Control * @dma_status: DMA Status * @reserved2: Reserved * @gbec_status: GMAC Status */ struct pch_gbe_tx_desc { … }; /** * struct pch_gbe_buffer - Buffer information * @skb: pointer to a socket buffer * @dma: DMA address * @time_stamp: time stamp * @length: data size */ struct pch_gbe_buffer { … }; /** * struct pch_gbe_tx_ring - tx ring information * @desc: pointer to the descriptor ring memory * @dma: physical address of the descriptor ring * @size: length of descriptor ring in bytes * @count: number of descriptors in the ring * @next_to_use: next descriptor to associate a buffer with * @next_to_clean: next descriptor to check for DD status bit * @buffer_info: array of buffer information structs */ struct pch_gbe_tx_ring { … }; /** * struct pch_gbe_rx_ring - rx ring information * @desc: pointer to the descriptor ring memory * @dma: physical address of the descriptor ring * @size: length of descriptor ring in bytes * @count: number of descriptors in the ring * @next_to_use: next descriptor to associate a buffer with * @next_to_clean: next descriptor to check for DD status bit * @buffer_info: array of buffer information structs */ struct pch_gbe_rx_ring { … }; /** * struct pch_gbe_hw_stats - Statistics counters collected by the MAC * @rx_packets: total packets received * @tx_packets: total packets transmitted * @rx_bytes: total bytes received * @tx_bytes: total bytes transmitted * @rx_errors: bad packets received * @tx_errors: packet transmit problems * @rx_dropped: no space in Linux buffers * @tx_dropped: no space available in Linux * @multicast: multicast packets received * @collisions: collisions * @rx_crc_errors: received packet with crc error * @rx_frame_errors: received frame alignment error * @rx_alloc_buff_failed: allocate failure of a receive buffer * @tx_length_errors: transmit length error * @tx_aborted_errors: transmit aborted error * @tx_carrier_errors: transmit carrier error * @tx_timeout_count: Number of transmit timeout * @tx_restart_count: Number of transmit restert * @intr_rx_dsc_empty_count: Interrupt count of receive descriptor empty * @intr_rx_frame_err_count: Interrupt count of receive frame error * @intr_rx_fifo_err_count: Interrupt count of receive FIFO error * @intr_rx_dma_err_count: Interrupt count of receive DMA error * @intr_tx_fifo_err_count: Interrupt count of transmit FIFO error * @intr_tx_dma_err_count: Interrupt count of transmit DMA error * @intr_tcpip_err_count: Interrupt count of TCP/IP Accelerator */ struct pch_gbe_hw_stats { … }; /** * struct pch_gbe_privdata - PCI Device ID driver data * @phy_tx_clk_delay: Bool, configure the PHY TX delay in software * @phy_disable_hibernate: Bool, disable PHY hibernation * @platform_init: Platform initialization callback, called from * probe, prior to PHY initialization. */ struct pch_gbe_privdata { … }; /** * struct pch_gbe_adapter - board specific private data structure * @stats_lock: Spinlock structure for status * @ethtool_lock: Spinlock structure for ethtool * @irq_sem: Semaphore for interrupt * @netdev: Pointer of network device structure * @pdev: Pointer of pci device structure * @polling_netdev: Pointer of polling network device structure * @napi: NAPI structure * @hw: Pointer of hardware structure * @stats: Hardware status * @reset_task: Reset task * @mii: MII information structure * @watchdog_timer: Watchdog timer list * @wake_up_evt: Wake up event * @config_space: Configuration space * @msg_enable: Driver message level * @led_status: LED status * @tx_ring: Pointer of Tx descriptor ring structure * @rx_ring: Pointer of Rx descriptor ring structure * @rx_buffer_len: Receive buffer length * @tx_queue_len: Transmit queue length * @pch_gbe_privdata: PCI Device ID driver_data */ struct pch_gbe_adapter { … }; #define pch_gbe_hw_to_adapter(hw) … /* pch_gbe_main.c */ int pch_gbe_up(struct pch_gbe_adapter *adapter); void pch_gbe_down(struct pch_gbe_adapter *adapter); void pch_gbe_reinit_locked(struct pch_gbe_adapter *adapter); void pch_gbe_reset(struct pch_gbe_adapter *adapter); int pch_gbe_setup_tx_resources(struct pch_gbe_adapter *adapter, struct pch_gbe_tx_ring *txdr); int pch_gbe_setup_rx_resources(struct pch_gbe_adapter *adapter, struct pch_gbe_rx_ring *rxdr); void pch_gbe_free_tx_resources(struct pch_gbe_adapter *adapter, struct pch_gbe_tx_ring *tx_ring); void pch_gbe_free_rx_resources(struct pch_gbe_adapter *adapter, struct pch_gbe_rx_ring *rx_ring); void pch_gbe_update_stats(struct pch_gbe_adapter *adapter); /* pch_gbe_param.c */ void pch_gbe_check_options(struct pch_gbe_adapter *adapter); /* pch_gbe_ethtool.c */ void pch_gbe_set_ethtool_ops(struct net_device *netdev); /* pch_gbe_mac.c */ s32 pch_gbe_mac_force_mac_fc(struct pch_gbe_hw *hw); u16 pch_gbe_mac_ctrl_miim(struct pch_gbe_hw *hw, u32 addr, u32 dir, u32 reg, u16 data); #endif /* _PCH_GBE_H_ */
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