/* SPDX-License-Identifier: GPL-2.0-only */ /**************************************************************************** * Driver for Solarflare network controllers and boards * Copyright 2005-2006 Fen Systems Ltd. * Copyright 2006-2013 Solarflare Communications Inc. */ #ifndef EF4_NIC_H #define EF4_NIC_H #include <linux/net_tstamp.h> #include <linux/i2c-algo-bit.h> #include "net_driver.h" #include "efx.h" enum { … }; static inline int ef4_nic_rev(struct ef4_nic *efx) { … } u32 ef4_farch_fpga_ver(struct ef4_nic *efx); /* NIC has two interlinked PCI functions for the same port. */ static inline bool ef4_nic_is_dual_func(struct ef4_nic *efx) { … } /* Read the current event from the event queue */ static inline ef4_qword_t *ef4_event(struct ef4_channel *channel, unsigned int index) { … } /* See if an event is present * * We check both the high and low dword of the event for all ones. We * wrote all ones when we cleared the event, and no valid event can * have all ones in either its high or low dwords. This approach is * robust against reordering. * * Note that using a single 64-bit comparison is incorrect; even * though the CPU read will be atomic, the DMA write may not be. */ static inline int ef4_event_present(ef4_qword_t *event) { … } /* Returns a pointer to the specified transmit descriptor in the TX * descriptor queue belonging to the specified channel. */ static inline ef4_qword_t * ef4_tx_desc(struct ef4_tx_queue *tx_queue, unsigned int index) { … } /* Get partner of a TX queue, seen as part of the same net core queue */ static inline struct ef4_tx_queue *ef4_tx_queue_partner(struct ef4_tx_queue *tx_queue) { … } /* Report whether this TX queue would be empty for the given write_count. * May return false negative. */ static inline bool __ef4_nic_tx_is_empty(struct ef4_tx_queue *tx_queue, unsigned int write_count) { … } /* Decide whether to push a TX descriptor to the NIC vs merely writing * the doorbell. This can reduce latency when we are adding a single * descriptor to an empty queue, but is otherwise pointless. Further, * Falcon and Siena have hardware bugs (SF bug 33851) that may be * triggered if we don't check this. * We use the write_count used for the last doorbell push, to get the * NIC's view of the tx queue. */ static inline bool ef4_nic_may_push_tx_desc(struct ef4_tx_queue *tx_queue, unsigned int write_count) { … } /* Returns a pointer to the specified descriptor in the RX descriptor queue */ static inline ef4_qword_t * ef4_rx_desc(struct ef4_rx_queue *rx_queue, unsigned int index) { … } enum { … }; #define FALCON_XMAC_LOOPBACKS … /* Alignment of PCIe DMA boundaries (4KB) */ #define EF4_PAGE_SIZE … /* Size and alignment of buffer table entries (same) */ #define EF4_BUF_SIZE … /* NIC-generic software stats */ enum { … }; /** * struct falcon_board_type - board operations and type information * @id: Board type id, as found in NVRAM * @init: Allocate resources and initialise peripheral hardware * @init_phy: Do board-specific PHY initialisation * @fini: Shut down hardware and free resources * @set_id_led: Set state of identifying LED or revert to automatic function * @monitor: Board-specific health check function */ struct falcon_board_type { … }; /** * struct falcon_board - board information * @type: Type of board * @major: Major rev. ('A', 'B' ...) * @minor: Minor rev. (0, 1, ...) * @i2c_adap: I2C adapter for on-board peripherals * @i2c_data: Data for bit-banging algorithm * @hwmon_client: I2C client for hardware monitor * @ioexp_client: I2C client for power/port control */ struct falcon_board { … }; /** * struct falcon_spi_device - a Falcon SPI (Serial Peripheral Interface) device * @device_id: Controller's id for the device * @size: Size (in bytes) * @addr_len: Number of address bytes in read/write commands * @munge_address: Flag whether addresses should be munged. * Some devices with 9-bit addresses (e.g. AT25040A EEPROM) * use bit 3 of the command byte as address bit A8, rather * than having a two-byte address. If this flag is set, then * commands should be munged in this way. * @erase_command: Erase command (or 0 if sector erase not needed). * @erase_size: Erase sector size (in bytes) * Erase commands affect sectors with this size and alignment. * This must be a power of two. * @block_size: Write block size (in bytes). * Write commands are limited to blocks with this size and alignment. */ struct falcon_spi_device { … }; static inline bool falcon_spi_present(const struct falcon_spi_device *spi) { … } enum { … }; /** * struct falcon_nic_data - Falcon NIC state * @pci_dev2: Secondary function of Falcon A * @efx: ef4_nic pointer * @board: Board state and functions * @stats: Hardware statistics * @stats_disable_count: Nest count for disabling statistics fetches * @stats_pending: Is there a pending DMA of MAC statistics. * @stats_timer: A timer for regularly fetching MAC statistics. * @spi_flash: SPI flash device * @spi_eeprom: SPI EEPROM device * @spi_lock: SPI bus lock * @mdio_lock: MDIO bus lock * @xmac_poll_required: XMAC link state needs polling */ struct falcon_nic_data { … }; static inline struct falcon_board *falcon_board(struct ef4_nic *efx) { … } struct kernel_ethtool_ts_info; extern const struct ef4_nic_type falcon_a1_nic_type; extern const struct ef4_nic_type falcon_b0_nic_type; /************************************************************************** * * Externs * ************************************************************************** */ int falcon_probe_board(struct ef4_nic *efx, u16 revision_info); /* TX data path */ static inline int ef4_nic_probe_tx(struct ef4_tx_queue *tx_queue) { … } static inline void ef4_nic_init_tx(struct ef4_tx_queue *tx_queue) { … } static inline void ef4_nic_remove_tx(struct ef4_tx_queue *tx_queue) { … } static inline void ef4_nic_push_buffers(struct ef4_tx_queue *tx_queue) { … } /* RX data path */ static inline int ef4_nic_probe_rx(struct ef4_rx_queue *rx_queue) { … } static inline void ef4_nic_init_rx(struct ef4_rx_queue *rx_queue) { … } static inline void ef4_nic_remove_rx(struct ef4_rx_queue *rx_queue) { … } static inline void ef4_nic_notify_rx_desc(struct ef4_rx_queue *rx_queue) { … } static inline void ef4_nic_generate_fill_event(struct ef4_rx_queue *rx_queue) { … } /* Event data path */ static inline int ef4_nic_probe_eventq(struct ef4_channel *channel) { … } static inline int ef4_nic_init_eventq(struct ef4_channel *channel) { … } static inline void ef4_nic_fini_eventq(struct ef4_channel *channel) { … } static inline void ef4_nic_remove_eventq(struct ef4_channel *channel) { … } static inline int ef4_nic_process_eventq(struct ef4_channel *channel, int quota) { … } static inline void ef4_nic_eventq_read_ack(struct ef4_channel *channel) { … } void ef4_nic_event_test_start(struct ef4_channel *channel); /* queue operations */ int ef4_farch_tx_probe(struct ef4_tx_queue *tx_queue); void ef4_farch_tx_init(struct ef4_tx_queue *tx_queue); void ef4_farch_tx_fini(struct ef4_tx_queue *tx_queue); void ef4_farch_tx_remove(struct ef4_tx_queue *tx_queue); void ef4_farch_tx_write(struct ef4_tx_queue *tx_queue); unsigned int ef4_farch_tx_limit_len(struct ef4_tx_queue *tx_queue, dma_addr_t dma_addr, unsigned int len); int ef4_farch_rx_probe(struct ef4_rx_queue *rx_queue); void ef4_farch_rx_init(struct ef4_rx_queue *rx_queue); void ef4_farch_rx_fini(struct ef4_rx_queue *rx_queue); void ef4_farch_rx_remove(struct ef4_rx_queue *rx_queue); void ef4_farch_rx_write(struct ef4_rx_queue *rx_queue); void ef4_farch_rx_defer_refill(struct ef4_rx_queue *rx_queue); int ef4_farch_ev_probe(struct ef4_channel *channel); int ef4_farch_ev_init(struct ef4_channel *channel); void ef4_farch_ev_fini(struct ef4_channel *channel); void ef4_farch_ev_remove(struct ef4_channel *channel); int ef4_farch_ev_process(struct ef4_channel *channel, int quota); void ef4_farch_ev_read_ack(struct ef4_channel *channel); void ef4_farch_ev_test_generate(struct ef4_channel *channel); /* filter operations */ int ef4_farch_filter_table_probe(struct ef4_nic *efx); void ef4_farch_filter_table_restore(struct ef4_nic *efx); void ef4_farch_filter_table_remove(struct ef4_nic *efx); void ef4_farch_filter_update_rx_scatter(struct ef4_nic *efx); s32 ef4_farch_filter_insert(struct ef4_nic *efx, struct ef4_filter_spec *spec, bool replace); int ef4_farch_filter_remove_safe(struct ef4_nic *efx, enum ef4_filter_priority priority, u32 filter_id); int ef4_farch_filter_get_safe(struct ef4_nic *efx, enum ef4_filter_priority priority, u32 filter_id, struct ef4_filter_spec *); int ef4_farch_filter_clear_rx(struct ef4_nic *efx, enum ef4_filter_priority priority); u32 ef4_farch_filter_count_rx_used(struct ef4_nic *efx, enum ef4_filter_priority priority); u32 ef4_farch_filter_get_rx_id_limit(struct ef4_nic *efx); s32 ef4_farch_filter_get_rx_ids(struct ef4_nic *efx, enum ef4_filter_priority priority, u32 *buf, u32 size); #ifdef CONFIG_RFS_ACCEL s32 ef4_farch_filter_rfs_insert(struct ef4_nic *efx, struct ef4_filter_spec *spec); bool ef4_farch_filter_rfs_expire_one(struct ef4_nic *efx, u32 flow_id, unsigned int index); #endif void ef4_farch_filter_sync_rx_mode(struct ef4_nic *efx); bool ef4_nic_event_present(struct ef4_channel *channel); /* Some statistics are computed as A - B where A and B each increase * linearly with some hardware counter(s) and the counters are read * asynchronously. If the counters contributing to B are always read * after those contributing to A, the computed value may be lower than * the true value by some variable amount, and may decrease between * subsequent computations. * * We should never allow statistics to decrease or to exceed the true * value. Since the computed value will never be greater than the * true value, we can achieve this by only storing the computed value * when it increases. */ static inline void ef4_update_diff_stat(u64 *stat, u64 diff) { … } /* Interrupts */ int ef4_nic_init_interrupt(struct ef4_nic *efx); int ef4_nic_irq_test_start(struct ef4_nic *efx); void ef4_nic_fini_interrupt(struct ef4_nic *efx); void ef4_farch_irq_enable_master(struct ef4_nic *efx); int ef4_farch_irq_test_generate(struct ef4_nic *efx); void ef4_farch_irq_disable_master(struct ef4_nic *efx); irqreturn_t ef4_farch_msi_interrupt(int irq, void *dev_id); irqreturn_t ef4_farch_legacy_interrupt(int irq, void *dev_id); irqreturn_t ef4_farch_fatal_interrupt(struct ef4_nic *efx); static inline int ef4_nic_event_test_irq_cpu(struct ef4_channel *channel) { … } static inline int ef4_nic_irq_test_irq_cpu(struct ef4_nic *efx) { … } /* Global Resources */ int ef4_nic_flush_queues(struct ef4_nic *efx); int ef4_farch_fini_dmaq(struct ef4_nic *efx); void ef4_farch_finish_flr(struct ef4_nic *efx); void falcon_start_nic_stats(struct ef4_nic *efx); void falcon_stop_nic_stats(struct ef4_nic *efx); int falcon_reset_xaui(struct ef4_nic *efx); void ef4_farch_dimension_resources(struct ef4_nic *efx, unsigned sram_lim_qw); void ef4_farch_init_common(struct ef4_nic *efx); void ef4_farch_rx_push_indir_table(struct ef4_nic *efx); int ef4_nic_alloc_buffer(struct ef4_nic *efx, struct ef4_buffer *buffer, unsigned int len, gfp_t gfp_flags); void ef4_nic_free_buffer(struct ef4_nic *efx, struct ef4_buffer *buffer); /* Tests */ struct ef4_farch_register_test { … }; int ef4_farch_test_registers(struct ef4_nic *efx, const struct ef4_farch_register_test *regs, size_t n_regs); size_t ef4_nic_get_regs_len(struct ef4_nic *efx); void ef4_nic_get_regs(struct ef4_nic *efx, void *buf); size_t ef4_nic_describe_stats(const struct ef4_hw_stat_desc *desc, size_t count, const unsigned long *mask, u8 *names); void ef4_nic_update_stats(const struct ef4_hw_stat_desc *desc, size_t count, const unsigned long *mask, u64 *stats, const void *dma_buf, bool accumulate); void ef4_nic_fix_nodesc_drop_stat(struct ef4_nic *efx, u64 *stat); #define EF4_MAX_FLUSH_TIME … void ef4_farch_generate_event(struct ef4_nic *efx, unsigned int evq, ef4_qword_t *event); #endif /* EF4_NIC_H */
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