// SPDX-License-Identifier: GPL-2.0-only /**************************************************************************** * Driver for Solarflare network controllers and boards * Copyright 2006-2011 Solarflare Communications Inc. */ /* * Driver for Transwitch/Mysticom CX4 retimer * see www.transwitch.com, part is TXC-43128 */ #include <linux/delay.h> #include <linux/slab.h> #include "efx.h" #include "mdio_10g.h" #include "phy.h" #include "nic.h" /* We expect these MMDs to be in the package */ #define TXC_REQUIRED_DEVS … #define TXC_LOOPBACKS … /************************************************************************** * * Compile-time config * ************************************************************************** */ #define TXCNAME … /* Total length of time we'll wait for the PHY to come out of reset (ms) */ #define TXC_MAX_RESET_TIME … /* Interval between checks (ms) */ #define TXC_RESET_WAIT … /* How long to run BIST (us) */ #define TXC_BIST_DURATION … /************************************************************************** * * Register definitions * ************************************************************************** */ /* Command register */ #define TXC_GLRGS_GLCMD … /* Useful bits in command register */ /* Lane power-down */ #define TXC_GLCMD_L01PD_LBN … #define TXC_GLCMD_L23PD_LBN … /* Limited SW reset: preserves configuration but * initiates a logic reset. Self-clearing */ #define TXC_GLCMD_LMTSWRST_LBN … /* Signal Quality Control */ #define TXC_GLRGS_GSGQLCTL … /* Enable bit */ #define TXC_GSGQLCT_SGQLEN_LBN … /* Lane selection */ #define TXC_GSGQLCT_LNSL_LBN … #define TXC_GSGQLCT_LNSL_WIDTH … /* Analog TX control */ #define TXC_ALRGS_ATXCTL … /* Lane power-down */ #define TXC_ATXCTL_TXPD3_LBN … #define TXC_ATXCTL_TXPD2_LBN … #define TXC_ATXCTL_TXPD1_LBN … #define TXC_ATXCTL_TXPD0_LBN … /* Amplitude on lanes 0, 1 */ #define TXC_ALRGS_ATXAMP0 … /* Amplitude on lanes 2, 3 */ #define TXC_ALRGS_ATXAMP1 … /* Bit position of value for lane 0 (or 2) */ #define TXC_ATXAMP_LANE02_LBN … /* Bit position of value for lane 1 (or 3) */ #define TXC_ATXAMP_LANE13_LBN … #define TXC_ATXAMP_1280_mV … #define TXC_ATXAMP_1200_mV … #define TXC_ATXAMP_1120_mV … #define TXC_ATXAMP_1060_mV … #define TXC_ATXAMP_0820_mV … #define TXC_ATXAMP_0720_mV … #define TXC_ATXAMP_0580_mV … #define TXC_ATXAMP_0440_mV … #define TXC_ATXAMP_0820_BOTH … #define TXC_ATXAMP_DEFAULT … /* Preemphasis on lanes 0, 1 */ #define TXC_ALRGS_ATXPRE0 … /* Preemphasis on lanes 2, 3 */ #define TXC_ALRGS_ATXPRE1 … #define TXC_ATXPRE_NONE … #define TXC_ATXPRE_DEFAULT … #define TXC_ALRGS_ARXCTL … /* Lane power-down */ #define TXC_ARXCTL_RXPD3_LBN … #define TXC_ARXCTL_RXPD2_LBN … #define TXC_ARXCTL_RXPD1_LBN … #define TXC_ARXCTL_RXPD0_LBN … /* Main control */ #define TXC_MRGS_CTL … /* Bits in main control */ #define TXC_MCTL_RESET_LBN … #define TXC_MCTL_TXLED_LBN … #define TXC_MCTL_RXLED_LBN … /* GPIO output */ #define TXC_GPIO_OUTPUT … #define TXC_GPIO_DIR … /* Vendor-specific BIST registers */ #define TXC_BIST_CTL … #define TXC_BIST_TXFRMCNT … #define TXC_BIST_RX0FRMCNT … #define TXC_BIST_RX1FRMCNT … #define TXC_BIST_RX2FRMCNT … #define TXC_BIST_RX3FRMCNT … #define TXC_BIST_RX0ERRCNT … #define TXC_BIST_RX1ERRCNT … #define TXC_BIST_RX2ERRCNT … #define TXC_BIST_RX3ERRCNT … /* BIST type (controls bit patter in test) */ #define TXC_BIST_CTRL_TYPE_LBN … #define TXC_BIST_CTRL_TYPE_TSD … #define TXC_BIST_CTRL_TYPE_CRP … #define TXC_BIST_CTRL_TYPE_CJP … #define TXC_BIST_CTRL_TYPE_TSR … /* Set this to 1 for 10 bit and 0 for 8 bit */ #define TXC_BIST_CTRL_B10EN_LBN … /* Enable BIST (write 0 to disable) */ #define TXC_BIST_CTRL_ENAB_LBN … /* Stop BIST (self-clears when stop complete) */ #define TXC_BIST_CTRL_STOP_LBN … /* Start BIST (cleared by writing 1 to STOP) */ #define TXC_BIST_CTRL_STRT_LBN … /* Mt. Diablo test configuration */ #define TXC_MTDIABLO_CTRL … #define TXC_MTDIABLO_CTRL_PMA_LOOP_LBN … struct txc43128_data { … }; /* The PHY sometimes needs a reset to bring the link back up. So long as * it reports link down, we reset it every 5 seconds. */ #define BUG10934_RESET_INTERVAL … /* Perform a reset that doesn't clear configuration changes */ static void txc_reset_logic(struct ef4_nic *efx); /* Set the output value of a gpio */ void falcon_txc_set_gpio_val(struct ef4_nic *efx, int pin, int on) { … } /* Set up the GPIO direction register */ void falcon_txc_set_gpio_dir(struct ef4_nic *efx, int pin, int dir) { … } /* Reset the PMA/PMD MMD. The documentation is explicit that this does a * global reset (it's less clear what reset of other MMDs does).*/ static int txc_reset_phy(struct ef4_nic *efx) { … } /* Run a single BIST on one MMD */ static int txc_bist_one(struct ef4_nic *efx, int mmd, int test) { … } static int txc_bist(struct ef4_nic *efx) { … } /* Push the non-configurable defaults into the PHY. This must be * done after every full reset */ static void txc_apply_defaults(struct ef4_nic *efx) { … } static int txc43128_phy_probe(struct ef4_nic *efx) { … } /* Initialisation entry point for this PHY driver */ static int txc43128_phy_init(struct ef4_nic *efx) { … } /* Set the lane power down state in the global registers */ static void txc_glrgs_lane_power(struct ef4_nic *efx, int mmd) { … } /* Set the lane power down state in the analog control registers */ static void txc_analog_lane_power(struct ef4_nic *efx, int mmd) { … } static void txc_set_power(struct ef4_nic *efx) { … } static void txc_reset_logic_mmd(struct ef4_nic *efx, int mmd) { … } /* Perform a logic reset. This preserves the configuration registers * and is needed for some configuration changes to take effect */ static void txc_reset_logic(struct ef4_nic *efx) { … } static bool txc43128_phy_read_link(struct ef4_nic *efx) { … } static int txc43128_phy_reconfigure(struct ef4_nic *efx) { … } static void txc43128_phy_fini(struct ef4_nic *efx) { … } static void txc43128_phy_remove(struct ef4_nic *efx) { … } /* Periodic callback: this exists mainly to poll link status as we * don't use LASI interrupts */ static bool txc43128_phy_poll(struct ef4_nic *efx) { … } static const char *const txc43128_test_names[] = …; static const char *txc43128_test_name(struct ef4_nic *efx, unsigned int index) { … } static int txc43128_run_tests(struct ef4_nic *efx, int *results, unsigned flags) { … } static void txc43128_get_link_ksettings(struct ef4_nic *efx, struct ethtool_link_ksettings *cmd) { … } const struct ef4_phy_operations falcon_txc_phy_ops = …;
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