/* SPDX-License-Identifier: GPL-2.0-only */ /**************************************************************************** * Driver for Solarflare network controllers and boards * Copyright 2005-2006 Fen Systems Ltd. * Copyright 2006-2012 Solarflare Communications Inc. */ #ifndef EFX_FARCH_REGS_H #define EFX_FARCH_REGS_H /* * Falcon hardware architecture definitions have a name prefix following * the format: * * F<type>_<min-rev><max-rev>_ * * The following <type> strings are used: * * MMIO register MC register Host memory structure * ------------------------------------------------------------- * Address R MCR * Bitfield RF MCRF SF * Enumerator FE MCFE SE * * <min-rev> is the first revision to which the definition applies: * * A: Falcon A1 (SFC4000AB) * B: Falcon B0 (SFC4000BA) * C: Siena A0 (SFL9021AA) * * If the definition has been changed or removed in later revisions * then <max-rev> is the last revision to which the definition applies; * otherwise it is "Z". */ /************************************************************************** * * Falcon/Siena registers and descriptors * ************************************************************************** */ /* ADR_REGION_REG: Address region register */ #define FR_AZ_ADR_REGION … #define FRF_AZ_ADR_REGION3_LBN … #define FRF_AZ_ADR_REGION3_WIDTH … #define FRF_AZ_ADR_REGION2_LBN … #define FRF_AZ_ADR_REGION2_WIDTH … #define FRF_AZ_ADR_REGION1_LBN … #define FRF_AZ_ADR_REGION1_WIDTH … #define FRF_AZ_ADR_REGION0_LBN … #define FRF_AZ_ADR_REGION0_WIDTH … /* INT_EN_REG_KER: Kernel driver Interrupt enable register */ #define FR_AZ_INT_EN_KER … #define FRF_AZ_KER_INT_LEVE_SEL_LBN … #define FRF_AZ_KER_INT_LEVE_SEL_WIDTH … #define FRF_AZ_KER_INT_CHAR_LBN … #define FRF_AZ_KER_INT_CHAR_WIDTH … #define FRF_AZ_KER_INT_KER_LBN … #define FRF_AZ_KER_INT_KER_WIDTH … #define FRF_AZ_DRV_INT_EN_KER_LBN … #define FRF_AZ_DRV_INT_EN_KER_WIDTH … /* INT_EN_REG_CHAR: Char Driver interrupt enable register */ #define FR_BZ_INT_EN_CHAR … #define FRF_BZ_CHAR_INT_LEVE_SEL_LBN … #define FRF_BZ_CHAR_INT_LEVE_SEL_WIDTH … #define FRF_BZ_CHAR_INT_CHAR_LBN … #define FRF_BZ_CHAR_INT_CHAR_WIDTH … #define FRF_BZ_CHAR_INT_KER_LBN … #define FRF_BZ_CHAR_INT_KER_WIDTH … #define FRF_BZ_DRV_INT_EN_CHAR_LBN … #define FRF_BZ_DRV_INT_EN_CHAR_WIDTH … /* INT_ADR_REG_KER: Interrupt host address for Kernel driver */ #define FR_AZ_INT_ADR_KER … #define FRF_AZ_NORM_INT_VEC_DIS_KER_LBN … #define FRF_AZ_NORM_INT_VEC_DIS_KER_WIDTH … #define FRF_AZ_INT_ADR_KER_LBN … #define FRF_AZ_INT_ADR_KER_WIDTH … /* INT_ADR_REG_CHAR: Interrupt host address for Char driver */ #define FR_BZ_INT_ADR_CHAR … #define FRF_BZ_NORM_INT_VEC_DIS_CHAR_LBN … #define FRF_BZ_NORM_INT_VEC_DIS_CHAR_WIDTH … #define FRF_BZ_INT_ADR_CHAR_LBN … #define FRF_BZ_INT_ADR_CHAR_WIDTH … /* INT_ACK_KER: Kernel interrupt acknowledge register */ #define FR_AA_INT_ACK_KER … #define FRF_AA_INT_ACK_KER_FIELD_LBN … #define FRF_AA_INT_ACK_KER_FIELD_WIDTH … /* INT_ISR0_REG: Function 0 Interrupt Acknowledge Status register */ #define FR_BZ_INT_ISR0 … #define FRF_BZ_INT_ISR_REG_LBN … #define FRF_BZ_INT_ISR_REG_WIDTH … /* HW_INIT_REG: Hardware initialization register */ #define FR_AZ_HW_INIT … #define FRF_BB_BDMRD_CPLF_FULL_LBN … #define FRF_BB_BDMRD_CPLF_FULL_WIDTH … #define FRF_BB_PCIE_CPL_TIMEOUT_CTRL_LBN … #define FRF_BB_PCIE_CPL_TIMEOUT_CTRL_WIDTH … #define FRF_CZ_TX_MRG_TAGS_LBN … #define FRF_CZ_TX_MRG_TAGS_WIDTH … #define FRF_AB_TRGT_MASK_ALL_LBN … #define FRF_AB_TRGT_MASK_ALL_WIDTH … #define FRF_AZ_DOORBELL_DROP_LBN … #define FRF_AZ_DOORBELL_DROP_WIDTH … #define FRF_AB_TX_RREQ_MASK_EN_LBN … #define FRF_AB_TX_RREQ_MASK_EN_WIDTH … #define FRF_AB_PE_EIDLE_DIS_LBN … #define FRF_AB_PE_EIDLE_DIS_WIDTH … #define FRF_AA_FC_BLOCKING_EN_LBN … #define FRF_AA_FC_BLOCKING_EN_WIDTH … #define FRF_BZ_B2B_REQ_EN_LBN … #define FRF_BZ_B2B_REQ_EN_WIDTH … #define FRF_AA_B2B_REQ_EN_LBN … #define FRF_AA_B2B_REQ_EN_WIDTH … #define FRF_BB_FC_BLOCKING_EN_LBN … #define FRF_BB_FC_BLOCKING_EN_WIDTH … #define FRF_AZ_POST_WR_MASK_LBN … #define FRF_AZ_POST_WR_MASK_WIDTH … #define FRF_AZ_TLP_TC_LBN … #define FRF_AZ_TLP_TC_WIDTH … #define FRF_AZ_TLP_ATTR_LBN … #define FRF_AZ_TLP_ATTR_WIDTH … #define FRF_AB_INTB_VEC_LBN … #define FRF_AB_INTB_VEC_WIDTH … #define FRF_AB_INTA_VEC_LBN … #define FRF_AB_INTA_VEC_WIDTH … #define FRF_AZ_WD_TIMER_LBN … #define FRF_AZ_WD_TIMER_WIDTH … #define FRF_AZ_US_DISABLE_LBN … #define FRF_AZ_US_DISABLE_WIDTH … #define FRF_AZ_TLP_EP_LBN … #define FRF_AZ_TLP_EP_WIDTH … #define FRF_AZ_ATTR_SEL_LBN … #define FRF_AZ_ATTR_SEL_WIDTH … #define FRF_AZ_TD_SEL_LBN … #define FRF_AZ_TD_SEL_WIDTH … #define FRF_AZ_TLP_TD_LBN … #define FRF_AZ_TLP_TD_WIDTH … /* EE_SPI_HCMD_REG: SPI host command register */ #define FR_AB_EE_SPI_HCMD … #define FRF_AB_EE_SPI_HCMD_CMD_EN_LBN … #define FRF_AB_EE_SPI_HCMD_CMD_EN_WIDTH … #define FRF_AB_EE_WR_TIMER_ACTIVE_LBN … #define FRF_AB_EE_WR_TIMER_ACTIVE_WIDTH … #define FRF_AB_EE_SPI_HCMD_SF_SEL_LBN … #define FRF_AB_EE_SPI_HCMD_SF_SEL_WIDTH … #define FRF_AB_EE_SPI_HCMD_DABCNT_LBN … #define FRF_AB_EE_SPI_HCMD_DABCNT_WIDTH … #define FRF_AB_EE_SPI_HCMD_READ_LBN … #define FRF_AB_EE_SPI_HCMD_READ_WIDTH … #define FRF_AB_EE_SPI_HCMD_DUBCNT_LBN … #define FRF_AB_EE_SPI_HCMD_DUBCNT_WIDTH … #define FRF_AB_EE_SPI_HCMD_ADBCNT_LBN … #define FRF_AB_EE_SPI_HCMD_ADBCNT_WIDTH … #define FRF_AB_EE_SPI_HCMD_ENC_LBN … #define FRF_AB_EE_SPI_HCMD_ENC_WIDTH … /* USR_EV_CFG: User Level Event Configuration register */ #define FR_CZ_USR_EV_CFG … #define FRF_CZ_USREV_DIS_LBN … #define FRF_CZ_USREV_DIS_WIDTH … #define FRF_CZ_DFLT_EVQ_LBN … #define FRF_CZ_DFLT_EVQ_WIDTH … /* EE_SPI_HADR_REG: SPI host address register */ #define FR_AB_EE_SPI_HADR … #define FRF_AB_EE_SPI_HADR_DUBYTE_LBN … #define FRF_AB_EE_SPI_HADR_DUBYTE_WIDTH … #define FRF_AB_EE_SPI_HADR_ADR_LBN … #define FRF_AB_EE_SPI_HADR_ADR_WIDTH … /* EE_SPI_HDATA_REG: SPI host data register */ #define FR_AB_EE_SPI_HDATA … #define FRF_AB_EE_SPI_HDATA3_LBN … #define FRF_AB_EE_SPI_HDATA3_WIDTH … #define FRF_AB_EE_SPI_HDATA2_LBN … #define FRF_AB_EE_SPI_HDATA2_WIDTH … #define FRF_AB_EE_SPI_HDATA1_LBN … #define FRF_AB_EE_SPI_HDATA1_WIDTH … #define FRF_AB_EE_SPI_HDATA0_LBN … #define FRF_AB_EE_SPI_HDATA0_WIDTH … /* EE_BASE_PAGE_REG: Expansion ROM base mirror register */ #define FR_AB_EE_BASE_PAGE … #define FRF_AB_EE_EXPROM_MASK_LBN … #define FRF_AB_EE_EXPROM_MASK_WIDTH … #define FRF_AB_EE_EXP_ROM_WINDOW_BASE_LBN … #define FRF_AB_EE_EXP_ROM_WINDOW_BASE_WIDTH … /* EE_VPD_CFG0_REG: SPI/VPD configuration register 0 */ #define FR_AB_EE_VPD_CFG0 … #define FRF_AB_EE_SF_FASTRD_EN_LBN … #define FRF_AB_EE_SF_FASTRD_EN_WIDTH … #define FRF_AB_EE_SF_CLOCK_DIV_LBN … #define FRF_AB_EE_SF_CLOCK_DIV_WIDTH … #define FRF_AB_EE_VPD_WIP_POLL_LBN … #define FRF_AB_EE_VPD_WIP_POLL_WIDTH … #define FRF_AB_EE_EE_CLOCK_DIV_LBN … #define FRF_AB_EE_EE_CLOCK_DIV_WIDTH … #define FRF_AB_EE_EE_WR_TMR_VALUE_LBN … #define FRF_AB_EE_EE_WR_TMR_VALUE_WIDTH … #define FRF_AB_EE_VPDW_LENGTH_LBN … #define FRF_AB_EE_VPDW_LENGTH_WIDTH … #define FRF_AB_EE_VPDW_BASE_LBN … #define FRF_AB_EE_VPDW_BASE_WIDTH … #define FRF_AB_EE_VPD_WR_CMD_EN_LBN … #define FRF_AB_EE_VPD_WR_CMD_EN_WIDTH … #define FRF_AB_EE_VPD_BASE_LBN … #define FRF_AB_EE_VPD_BASE_WIDTH … #define FRF_AB_EE_VPD_LENGTH_LBN … #define FRF_AB_EE_VPD_LENGTH_WIDTH … #define FRF_AB_EE_VPD_AD_SIZE_LBN … #define FRF_AB_EE_VPD_AD_SIZE_WIDTH … #define FRF_AB_EE_VPD_ACCESS_ON_LBN … #define FRF_AB_EE_VPD_ACCESS_ON_WIDTH … #define FRF_AB_EE_VPD_ACCESS_BLOCK_LBN … #define FRF_AB_EE_VPD_ACCESS_BLOCK_WIDTH … #define FRF_AB_EE_VPD_DEV_SF_SEL_LBN … #define FRF_AB_EE_VPD_DEV_SF_SEL_WIDTH … #define FRF_AB_EE_VPD_EN_AD9_MODE_LBN … #define FRF_AB_EE_VPD_EN_AD9_MODE_WIDTH … #define FRF_AB_EE_VPD_EN_LBN … #define FRF_AB_EE_VPD_EN_WIDTH … /* EE_VPD_SW_CNTL_REG: VPD access SW control register */ #define FR_AB_EE_VPD_SW_CNTL … #define FRF_AB_EE_VPD_CYCLE_PENDING_LBN … #define FRF_AB_EE_VPD_CYCLE_PENDING_WIDTH … #define FRF_AB_EE_VPD_CYC_WRITE_LBN … #define FRF_AB_EE_VPD_CYC_WRITE_WIDTH … #define FRF_AB_EE_VPD_CYC_ADR_LBN … #define FRF_AB_EE_VPD_CYC_ADR_WIDTH … /* EE_VPD_SW_DATA_REG: VPD access SW data register */ #define FR_AB_EE_VPD_SW_DATA … #define FRF_AB_EE_VPD_CYC_DAT_LBN … #define FRF_AB_EE_VPD_CYC_DAT_WIDTH … /* PBMX_DBG_IADDR_REG: Capture Module address register */ #define FR_CZ_PBMX_DBG_IADDR … #define FRF_CZ_PBMX_DBG_IADDR_LBN … #define FRF_CZ_PBMX_DBG_IADDR_WIDTH … /* PCIE_CORE_INDIRECT_REG: Indirect Access to PCIE Core registers */ #define FR_BB_PCIE_CORE_INDIRECT … #define FRF_BB_PCIE_CORE_TARGET_DATA_LBN … #define FRF_BB_PCIE_CORE_TARGET_DATA_WIDTH … #define FRF_BB_PCIE_CORE_INDIRECT_ACCESS_DIR_LBN … #define FRF_BB_PCIE_CORE_INDIRECT_ACCESS_DIR_WIDTH … #define FRF_BB_PCIE_CORE_TARGET_REG_ADRS_LBN … #define FRF_BB_PCIE_CORE_TARGET_REG_ADRS_WIDTH … /* PBMX_DBG_IDATA_REG: Capture Module data register */ #define FR_CZ_PBMX_DBG_IDATA … #define FRF_CZ_PBMX_DBG_IDATA_LBN … #define FRF_CZ_PBMX_DBG_IDATA_WIDTH … /* NIC_STAT_REG: NIC status register */ #define FR_AB_NIC_STAT … #define FRF_BB_AER_DIS_LBN … #define FRF_BB_AER_DIS_WIDTH … #define FRF_BB_EE_STRAP_EN_LBN … #define FRF_BB_EE_STRAP_EN_WIDTH … #define FRF_BB_EE_STRAP_LBN … #define FRF_BB_EE_STRAP_WIDTH … #define FRF_BB_REVISION_ID_LBN … #define FRF_BB_REVISION_ID_WIDTH … #define FRF_AB_ONCHIP_SRAM_LBN … #define FRF_AB_ONCHIP_SRAM_WIDTH … #define FRF_AB_SF_PRST_LBN … #define FRF_AB_SF_PRST_WIDTH … #define FRF_AB_EE_PRST_LBN … #define FRF_AB_EE_PRST_WIDTH … #define FRF_AB_ATE_MODE_LBN … #define FRF_AB_ATE_MODE_WIDTH … #define FRF_AB_STRAP_PINS_LBN … #define FRF_AB_STRAP_PINS_WIDTH … /* GPIO_CTL_REG: GPIO control register */ #define FR_AB_GPIO_CTL … #define FRF_AB_GPIO_OUT3_LBN … #define FRF_AB_GPIO_OUT3_WIDTH … #define FRF_AB_GPIO_IN3_LBN … #define FRF_AB_GPIO_IN3_WIDTH … #define FRF_AB_GPIO_PWRUP_VALUE3_LBN … #define FRF_AB_GPIO_PWRUP_VALUE3_WIDTH … #define FRF_AB_GPIO_OUT2_LBN … #define FRF_AB_GPIO_OUT2_WIDTH … #define FRF_AB_GPIO_IN2_LBN … #define FRF_AB_GPIO_IN2_WIDTH … #define FRF_AB_GPIO_PWRUP_VALUE2_LBN … #define FRF_AB_GPIO_PWRUP_VALUE2_WIDTH … #define FRF_AB_GPIO15_OEN_LBN … #define FRF_AB_GPIO15_OEN_WIDTH … #define FRF_AB_GPIO14_OEN_LBN … #define FRF_AB_GPIO14_OEN_WIDTH … #define FRF_AB_GPIO13_OEN_LBN … #define FRF_AB_GPIO13_OEN_WIDTH … #define FRF_AB_GPIO12_OEN_LBN … #define FRF_AB_GPIO12_OEN_WIDTH … #define FRF_AB_GPIO11_OEN_LBN … #define FRF_AB_GPIO11_OEN_WIDTH … #define FRF_AB_GPIO10_OEN_LBN … #define FRF_AB_GPIO10_OEN_WIDTH … #define FRF_AB_GPIO9_OEN_LBN … #define FRF_AB_GPIO9_OEN_WIDTH … #define FRF_AB_GPIO8_OEN_LBN … #define FRF_AB_GPIO8_OEN_WIDTH … #define FRF_AB_GPIO15_OUT_LBN … #define FRF_AB_GPIO15_OUT_WIDTH … #define FRF_AB_GPIO14_OUT_LBN … #define FRF_AB_GPIO14_OUT_WIDTH … #define FRF_AB_GPIO13_OUT_LBN … #define FRF_AB_GPIO13_OUT_WIDTH … #define FRF_AB_GPIO12_OUT_LBN … #define FRF_AB_GPIO12_OUT_WIDTH … #define FRF_AB_GPIO11_OUT_LBN … #define FRF_AB_GPIO11_OUT_WIDTH … #define FRF_AB_GPIO10_OUT_LBN … #define FRF_AB_GPIO10_OUT_WIDTH … #define FRF_AB_GPIO9_OUT_LBN … #define FRF_AB_GPIO9_OUT_WIDTH … #define FRF_AB_GPIO8_OUT_LBN … #define FRF_AB_GPIO8_OUT_WIDTH … #define FRF_AB_GPIO15_IN_LBN … #define FRF_AB_GPIO15_IN_WIDTH … #define FRF_AB_GPIO14_IN_LBN … #define FRF_AB_GPIO14_IN_WIDTH … #define FRF_AB_GPIO13_IN_LBN … #define FRF_AB_GPIO13_IN_WIDTH … #define FRF_AB_GPIO12_IN_LBN … #define FRF_AB_GPIO12_IN_WIDTH … #define FRF_AB_GPIO11_IN_LBN … #define FRF_AB_GPIO11_IN_WIDTH … #define FRF_AB_GPIO10_IN_LBN … #define FRF_AB_GPIO10_IN_WIDTH … #define FRF_AB_GPIO9_IN_LBN … #define FRF_AB_GPIO9_IN_WIDTH … #define FRF_AB_GPIO8_IN_LBN … #define FRF_AB_GPIO8_IN_WIDTH … #define FRF_AB_GPIO15_PWRUP_VALUE_LBN … #define FRF_AB_GPIO15_PWRUP_VALUE_WIDTH … #define FRF_AB_GPIO14_PWRUP_VALUE_LBN … #define FRF_AB_GPIO14_PWRUP_VALUE_WIDTH … #define FRF_AB_GPIO13_PWRUP_VALUE_LBN … #define FRF_AB_GPIO13_PWRUP_VALUE_WIDTH … #define FRF_AB_GPIO12_PWRUP_VALUE_LBN … #define FRF_AB_GPIO12_PWRUP_VALUE_WIDTH … #define FRF_AB_GPIO11_PWRUP_VALUE_LBN … #define FRF_AB_GPIO11_PWRUP_VALUE_WIDTH … #define FRF_AB_GPIO10_PWRUP_VALUE_LBN … #define FRF_AB_GPIO10_PWRUP_VALUE_WIDTH … #define FRF_AB_GPIO9_PWRUP_VALUE_LBN … #define FRF_AB_GPIO9_PWRUP_VALUE_WIDTH … #define FRF_AB_GPIO8_PWRUP_VALUE_LBN … #define FRF_AB_GPIO8_PWRUP_VALUE_WIDTH … #define FRF_AB_CLK156_OUT_EN_LBN … #define FRF_AB_CLK156_OUT_EN_WIDTH … #define FRF_AB_USE_NIC_CLK_LBN … #define FRF_AB_USE_NIC_CLK_WIDTH … #define FRF_AB_GPIO5_OEN_LBN … #define FRF_AB_GPIO5_OEN_WIDTH … #define FRF_AB_GPIO4_OEN_LBN … #define FRF_AB_GPIO4_OEN_WIDTH … #define FRF_AB_GPIO3_OEN_LBN … #define FRF_AB_GPIO3_OEN_WIDTH … #define FRF_AB_GPIO2_OEN_LBN … #define FRF_AB_GPIO2_OEN_WIDTH … #define FRF_AB_GPIO1_OEN_LBN … #define FRF_AB_GPIO1_OEN_WIDTH … #define FRF_AB_GPIO0_OEN_LBN … #define FRF_AB_GPIO0_OEN_WIDTH … #define FRF_AB_GPIO7_OUT_LBN … #define FRF_AB_GPIO7_OUT_WIDTH … #define FRF_AB_GPIO6_OUT_LBN … #define FRF_AB_GPIO6_OUT_WIDTH … #define FRF_AB_GPIO5_OUT_LBN … #define FRF_AB_GPIO5_OUT_WIDTH … #define FRF_AB_GPIO4_OUT_LBN … #define FRF_AB_GPIO4_OUT_WIDTH … #define FRF_AB_GPIO3_OUT_LBN … #define FRF_AB_GPIO3_OUT_WIDTH … #define FRF_AB_GPIO2_OUT_LBN … #define FRF_AB_GPIO2_OUT_WIDTH … #define FRF_AB_GPIO1_OUT_LBN … #define FRF_AB_GPIO1_OUT_WIDTH … #define FRF_AB_GPIO0_OUT_LBN … #define FRF_AB_GPIO0_OUT_WIDTH … #define FRF_AB_GPIO7_IN_LBN … #define FRF_AB_GPIO7_IN_WIDTH … #define FRF_AB_GPIO6_IN_LBN … #define FRF_AB_GPIO6_IN_WIDTH … #define FRF_AB_GPIO5_IN_LBN … #define FRF_AB_GPIO5_IN_WIDTH … #define FRF_AB_GPIO4_IN_LBN … #define FRF_AB_GPIO4_IN_WIDTH … #define FRF_AB_GPIO3_IN_LBN … #define FRF_AB_GPIO3_IN_WIDTH … #define FRF_AB_GPIO2_IN_LBN … #define FRF_AB_GPIO2_IN_WIDTH … #define FRF_AB_GPIO1_IN_LBN … #define FRF_AB_GPIO1_IN_WIDTH … #define FRF_AB_GPIO0_IN_LBN … #define FRF_AB_GPIO0_IN_WIDTH … #define FRF_AB_GPIO7_PWRUP_VALUE_LBN … #define FRF_AB_GPIO7_PWRUP_VALUE_WIDTH … #define FRF_AB_GPIO6_PWRUP_VALUE_LBN … #define FRF_AB_GPIO6_PWRUP_VALUE_WIDTH … #define FRF_AB_GPIO5_PWRUP_VALUE_LBN … #define FRF_AB_GPIO5_PWRUP_VALUE_WIDTH … #define FRF_AB_GPIO4_PWRUP_VALUE_LBN … #define FRF_AB_GPIO4_PWRUP_VALUE_WIDTH … #define FRF_AB_GPIO3_PWRUP_VALUE_LBN … #define FRF_AB_GPIO3_PWRUP_VALUE_WIDTH … #define FRF_AB_GPIO2_PWRUP_VALUE_LBN … #define FRF_AB_GPIO2_PWRUP_VALUE_WIDTH … #define FRF_AB_GPIO1_PWRUP_VALUE_LBN … #define FRF_AB_GPIO1_PWRUP_VALUE_WIDTH … #define FRF_AB_GPIO0_PWRUP_VALUE_LBN … #define FRF_AB_GPIO0_PWRUP_VALUE_WIDTH … /* GLB_CTL_REG: Global control register */ #define FR_AB_GLB_CTL … #define FRF_AB_EXT_PHY_RST_CTL_LBN … #define FRF_AB_EXT_PHY_RST_CTL_WIDTH … #define FRF_AB_XAUI_SD_RST_CTL_LBN … #define FRF_AB_XAUI_SD_RST_CTL_WIDTH … #define FRF_AB_PCIE_SD_RST_CTL_LBN … #define FRF_AB_PCIE_SD_RST_CTL_WIDTH … #define FRF_AA_PCIX_RST_CTL_LBN … #define FRF_AA_PCIX_RST_CTL_WIDTH … #define FRF_BB_BIU_RST_CTL_LBN … #define FRF_BB_BIU_RST_CTL_WIDTH … #define FRF_AB_PCIE_STKY_RST_CTL_LBN … #define FRF_AB_PCIE_STKY_RST_CTL_WIDTH … #define FRF_AB_PCIE_NSTKY_RST_CTL_LBN … #define FRF_AB_PCIE_NSTKY_RST_CTL_WIDTH … #define FRF_AB_PCIE_CORE_RST_CTL_LBN … #define FRF_AB_PCIE_CORE_RST_CTL_WIDTH … #define FRF_AB_XGRX_RST_CTL_LBN … #define FRF_AB_XGRX_RST_CTL_WIDTH … #define FRF_AB_XGTX_RST_CTL_LBN … #define FRF_AB_XGTX_RST_CTL_WIDTH … #define FRF_AB_EM_RST_CTL_LBN … #define FRF_AB_EM_RST_CTL_WIDTH … #define FRF_AB_EV_RST_CTL_LBN … #define FRF_AB_EV_RST_CTL_WIDTH … #define FRF_AB_SR_RST_CTL_LBN … #define FRF_AB_SR_RST_CTL_WIDTH … #define FRF_AB_RX_RST_CTL_LBN … #define FRF_AB_RX_RST_CTL_WIDTH … #define FRF_AB_TX_RST_CTL_LBN … #define FRF_AB_TX_RST_CTL_WIDTH … #define FRF_AB_EE_RST_CTL_LBN … #define FRF_AB_EE_RST_CTL_WIDTH … #define FRF_AB_CS_RST_CTL_LBN … #define FRF_AB_CS_RST_CTL_WIDTH … #define FRF_AB_HOT_RST_CTL_LBN … #define FRF_AB_HOT_RST_CTL_WIDTH … #define FRF_AB_RST_EXT_PHY_LBN … #define FRF_AB_RST_EXT_PHY_WIDTH … #define FRF_AB_RST_XAUI_SD_LBN … #define FRF_AB_RST_XAUI_SD_WIDTH … #define FRF_AB_RST_PCIE_SD_LBN … #define FRF_AB_RST_PCIE_SD_WIDTH … #define FRF_AA_RST_PCIX_LBN … #define FRF_AA_RST_PCIX_WIDTH … #define FRF_BB_RST_BIU_LBN … #define FRF_BB_RST_BIU_WIDTH … #define FRF_AB_RST_PCIE_STKY_LBN … #define FRF_AB_RST_PCIE_STKY_WIDTH … #define FRF_AB_RST_PCIE_NSTKY_LBN … #define FRF_AB_RST_PCIE_NSTKY_WIDTH … #define FRF_AB_RST_PCIE_CORE_LBN … #define FRF_AB_RST_PCIE_CORE_WIDTH … #define FRF_AB_RST_XGRX_LBN … #define FRF_AB_RST_XGRX_WIDTH … #define FRF_AB_RST_XGTX_LBN … #define FRF_AB_RST_XGTX_WIDTH … #define FRF_AB_RST_EM_LBN … #define FRF_AB_RST_EM_WIDTH … #define FRF_AB_RST_EV_LBN … #define FRF_AB_RST_EV_WIDTH … #define FRF_AB_RST_SR_LBN … #define FRF_AB_RST_SR_WIDTH … #define FRF_AB_RST_RX_LBN … #define FRF_AB_RST_RX_WIDTH … #define FRF_AB_RST_TX_LBN … #define FRF_AB_RST_TX_WIDTH … #define FRF_AB_RST_SF_LBN … #define FRF_AB_RST_SF_WIDTH … #define FRF_AB_RST_CS_LBN … #define FRF_AB_RST_CS_WIDTH … #define FRF_AB_INT_RST_DUR_LBN … #define FRF_AB_INT_RST_DUR_WIDTH … #define FRF_AB_EXT_PHY_RST_DUR_LBN … #define FRF_AB_EXT_PHY_RST_DUR_WIDTH … #define FFE_AB_EXT_PHY_RST_DUR_10240US … #define FFE_AB_EXT_PHY_RST_DUR_5120US … #define FFE_AB_EXT_PHY_RST_DUR_2560US … #define FFE_AB_EXT_PHY_RST_DUR_1280US … #define FFE_AB_EXT_PHY_RST_DUR_640US … #define FFE_AB_EXT_PHY_RST_DUR_320US … #define FFE_AB_EXT_PHY_RST_DUR_160US … #define FFE_AB_EXT_PHY_RST_DUR_80US … #define FRF_AB_SWRST_LBN … #define FRF_AB_SWRST_WIDTH … /* FATAL_INTR_REG_KER: Fatal interrupt register for Kernel */ #define FR_AZ_FATAL_INTR_KER … #define FRF_CZ_SRAM_PERR_INT_P_KER_EN_LBN … #define FRF_CZ_SRAM_PERR_INT_P_KER_EN_WIDTH … #define FRF_AB_PCI_BUSERR_INT_KER_EN_LBN … #define FRF_AB_PCI_BUSERR_INT_KER_EN_WIDTH … #define FRF_CZ_MBU_PERR_INT_KER_EN_LBN … #define FRF_CZ_MBU_PERR_INT_KER_EN_WIDTH … #define FRF_AZ_SRAM_OOB_INT_KER_EN_LBN … #define FRF_AZ_SRAM_OOB_INT_KER_EN_WIDTH … #define FRF_AZ_BUFID_OOB_INT_KER_EN_LBN … #define FRF_AZ_BUFID_OOB_INT_KER_EN_WIDTH … #define FRF_AZ_MEM_PERR_INT_KER_EN_LBN … #define FRF_AZ_MEM_PERR_INT_KER_EN_WIDTH … #define FRF_AZ_RBUF_OWN_INT_KER_EN_LBN … #define FRF_AZ_RBUF_OWN_INT_KER_EN_WIDTH … #define FRF_AZ_TBUF_OWN_INT_KER_EN_LBN … #define FRF_AZ_TBUF_OWN_INT_KER_EN_WIDTH … #define FRF_AZ_RDESCQ_OWN_INT_KER_EN_LBN … #define FRF_AZ_RDESCQ_OWN_INT_KER_EN_WIDTH … #define FRF_AZ_TDESCQ_OWN_INT_KER_EN_LBN … #define FRF_AZ_TDESCQ_OWN_INT_KER_EN_WIDTH … #define FRF_AZ_EVQ_OWN_INT_KER_EN_LBN … #define FRF_AZ_EVQ_OWN_INT_KER_EN_WIDTH … #define FRF_AZ_EVF_OFLO_INT_KER_EN_LBN … #define FRF_AZ_EVF_OFLO_INT_KER_EN_WIDTH … #define FRF_AZ_ILL_ADR_INT_KER_EN_LBN … #define FRF_AZ_ILL_ADR_INT_KER_EN_WIDTH … #define FRF_AZ_SRM_PERR_INT_KER_EN_LBN … #define FRF_AZ_SRM_PERR_INT_KER_EN_WIDTH … #define FRF_CZ_SRAM_PERR_INT_P_KER_LBN … #define FRF_CZ_SRAM_PERR_INT_P_KER_WIDTH … #define FRF_AB_PCI_BUSERR_INT_KER_LBN … #define FRF_AB_PCI_BUSERR_INT_KER_WIDTH … #define FRF_CZ_MBU_PERR_INT_KER_LBN … #define FRF_CZ_MBU_PERR_INT_KER_WIDTH … #define FRF_AZ_SRAM_OOB_INT_KER_LBN … #define FRF_AZ_SRAM_OOB_INT_KER_WIDTH … #define FRF_AZ_BUFID_DC_OOB_INT_KER_LBN … #define FRF_AZ_BUFID_DC_OOB_INT_KER_WIDTH … #define FRF_AZ_MEM_PERR_INT_KER_LBN … #define FRF_AZ_MEM_PERR_INT_KER_WIDTH … #define FRF_AZ_RBUF_OWN_INT_KER_LBN … #define FRF_AZ_RBUF_OWN_INT_KER_WIDTH … #define FRF_AZ_TBUF_OWN_INT_KER_LBN … #define FRF_AZ_TBUF_OWN_INT_KER_WIDTH … #define FRF_AZ_RDESCQ_OWN_INT_KER_LBN … #define FRF_AZ_RDESCQ_OWN_INT_KER_WIDTH … #define FRF_AZ_TDESCQ_OWN_INT_KER_LBN … #define FRF_AZ_TDESCQ_OWN_INT_KER_WIDTH … #define FRF_AZ_EVQ_OWN_INT_KER_LBN … #define FRF_AZ_EVQ_OWN_INT_KER_WIDTH … #define FRF_AZ_EVF_OFLO_INT_KER_LBN … #define FRF_AZ_EVF_OFLO_INT_KER_WIDTH … #define FRF_AZ_ILL_ADR_INT_KER_LBN … #define FRF_AZ_ILL_ADR_INT_KER_WIDTH … #define FRF_AZ_SRM_PERR_INT_KER_LBN … #define FRF_AZ_SRM_PERR_INT_KER_WIDTH … /* FATAL_INTR_REG_CHAR: Fatal interrupt register for Char */ #define FR_BZ_FATAL_INTR_CHAR … #define FRF_CZ_SRAM_PERR_INT_P_CHAR_EN_LBN … #define FRF_CZ_SRAM_PERR_INT_P_CHAR_EN_WIDTH … #define FRF_BB_PCI_BUSERR_INT_CHAR_EN_LBN … #define FRF_BB_PCI_BUSERR_INT_CHAR_EN_WIDTH … #define FRF_CZ_MBU_PERR_INT_CHAR_EN_LBN … #define FRF_CZ_MBU_PERR_INT_CHAR_EN_WIDTH … #define FRF_BZ_SRAM_OOB_INT_CHAR_EN_LBN … #define FRF_BZ_SRAM_OOB_INT_CHAR_EN_WIDTH … #define FRF_BZ_BUFID_OOB_INT_CHAR_EN_LBN … #define FRF_BZ_BUFID_OOB_INT_CHAR_EN_WIDTH … #define FRF_BZ_MEM_PERR_INT_CHAR_EN_LBN … #define FRF_BZ_MEM_PERR_INT_CHAR_EN_WIDTH … #define FRF_BZ_RBUF_OWN_INT_CHAR_EN_LBN … #define FRF_BZ_RBUF_OWN_INT_CHAR_EN_WIDTH … #define FRF_BZ_TBUF_OWN_INT_CHAR_EN_LBN … #define FRF_BZ_TBUF_OWN_INT_CHAR_EN_WIDTH … #define FRF_BZ_RDESCQ_OWN_INT_CHAR_EN_LBN … #define FRF_BZ_RDESCQ_OWN_INT_CHAR_EN_WIDTH … #define FRF_BZ_TDESCQ_OWN_INT_CHAR_EN_LBN … #define FRF_BZ_TDESCQ_OWN_INT_CHAR_EN_WIDTH … #define FRF_BZ_EVQ_OWN_INT_CHAR_EN_LBN … #define FRF_BZ_EVQ_OWN_INT_CHAR_EN_WIDTH … #define FRF_BZ_EVF_OFLO_INT_CHAR_EN_LBN … #define FRF_BZ_EVF_OFLO_INT_CHAR_EN_WIDTH … #define FRF_BZ_ILL_ADR_INT_CHAR_EN_LBN … #define FRF_BZ_ILL_ADR_INT_CHAR_EN_WIDTH … #define FRF_BZ_SRM_PERR_INT_CHAR_EN_LBN … #define FRF_BZ_SRM_PERR_INT_CHAR_EN_WIDTH … #define FRF_CZ_SRAM_PERR_INT_P_CHAR_LBN … #define FRF_CZ_SRAM_PERR_INT_P_CHAR_WIDTH … #define FRF_BB_PCI_BUSERR_INT_CHAR_LBN … #define FRF_BB_PCI_BUSERR_INT_CHAR_WIDTH … #define FRF_CZ_MBU_PERR_INT_CHAR_LBN … #define FRF_CZ_MBU_PERR_INT_CHAR_WIDTH … #define FRF_BZ_SRAM_OOB_INT_CHAR_LBN … #define FRF_BZ_SRAM_OOB_INT_CHAR_WIDTH … #define FRF_BZ_BUFID_DC_OOB_INT_CHAR_LBN … #define FRF_BZ_BUFID_DC_OOB_INT_CHAR_WIDTH … #define FRF_BZ_MEM_PERR_INT_CHAR_LBN … #define FRF_BZ_MEM_PERR_INT_CHAR_WIDTH … #define FRF_BZ_RBUF_OWN_INT_CHAR_LBN … #define FRF_BZ_RBUF_OWN_INT_CHAR_WIDTH … #define FRF_BZ_TBUF_OWN_INT_CHAR_LBN … #define FRF_BZ_TBUF_OWN_INT_CHAR_WIDTH … #define FRF_BZ_RDESCQ_OWN_INT_CHAR_LBN … #define FRF_BZ_RDESCQ_OWN_INT_CHAR_WIDTH … #define FRF_BZ_TDESCQ_OWN_INT_CHAR_LBN … #define FRF_BZ_TDESCQ_OWN_INT_CHAR_WIDTH … #define FRF_BZ_EVQ_OWN_INT_CHAR_LBN … #define FRF_BZ_EVQ_OWN_INT_CHAR_WIDTH … #define FRF_BZ_EVF_OFLO_INT_CHAR_LBN … #define FRF_BZ_EVF_OFLO_INT_CHAR_WIDTH … #define FRF_BZ_ILL_ADR_INT_CHAR_LBN … #define FRF_BZ_ILL_ADR_INT_CHAR_WIDTH … #define FRF_BZ_SRM_PERR_INT_CHAR_LBN … #define FRF_BZ_SRM_PERR_INT_CHAR_WIDTH … /* DP_CTRL_REG: Datapath control register */ #define FR_BZ_DP_CTRL … #define FRF_BZ_FLS_EVQ_ID_LBN … #define FRF_BZ_FLS_EVQ_ID_WIDTH … /* MEM_STAT_REG: Memory status register */ #define FR_AZ_MEM_STAT … #define FRF_AB_MEM_PERR_VEC_LBN … #define FRF_AB_MEM_PERR_VEC_WIDTH … #define FRF_AB_MBIST_CORR_LBN … #define FRF_AB_MBIST_CORR_WIDTH … #define FRF_AB_MBIST_ERR_LBN … #define FRF_AB_MBIST_ERR_WIDTH … #define FRF_CZ_MEM_PERR_VEC_LBN … #define FRF_CZ_MEM_PERR_VEC_WIDTH … /* CS_DEBUG_REG: Debug register */ #define FR_AZ_CS_DEBUG … #define FRF_AB_GLB_DEBUG2_SEL_LBN … #define FRF_AB_GLB_DEBUG2_SEL_WIDTH … #define FRF_AB_DEBUG_BLK_SEL2_LBN … #define FRF_AB_DEBUG_BLK_SEL2_WIDTH … #define FRF_AB_DEBUG_BLK_SEL1_LBN … #define FRF_AB_DEBUG_BLK_SEL1_WIDTH … #define FRF_AB_DEBUG_BLK_SEL0_LBN … #define FRF_AB_DEBUG_BLK_SEL0_WIDTH … #define FRF_CZ_CS_PORT_NUM_LBN … #define FRF_CZ_CS_PORT_NUM_WIDTH … #define FRF_AB_MISC_DEBUG_ADDR_LBN … #define FRF_AB_MISC_DEBUG_ADDR_WIDTH … #define FRF_AB_SERDES_DEBUG_ADDR_LBN … #define FRF_AB_SERDES_DEBUG_ADDR_WIDTH … #define FRF_CZ_CS_PORT_FPE_LBN … #define FRF_CZ_CS_PORT_FPE_WIDTH … #define FRF_AB_EM_DEBUG_ADDR_LBN … #define FRF_AB_EM_DEBUG_ADDR_WIDTH … #define FRF_AB_SR_DEBUG_ADDR_LBN … #define FRF_AB_SR_DEBUG_ADDR_WIDTH … #define FRF_AB_EV_DEBUG_ADDR_LBN … #define FRF_AB_EV_DEBUG_ADDR_WIDTH … #define FRF_AB_RX_DEBUG_ADDR_LBN … #define FRF_AB_RX_DEBUG_ADDR_WIDTH … #define FRF_AB_TX_DEBUG_ADDR_LBN … #define FRF_AB_TX_DEBUG_ADDR_WIDTH … #define FRF_AB_CS_BIU_DEBUG_ADDR_LBN … #define FRF_AB_CS_BIU_DEBUG_ADDR_WIDTH … #define FRF_AZ_CS_DEBUG_EN_LBN … #define FRF_AZ_CS_DEBUG_EN_WIDTH … /* DRIVER_REG: Driver scratch register [0-7] */ #define FR_AZ_DRIVER … #define FR_AZ_DRIVER_STEP … #define FR_AZ_DRIVER_ROWS … #define FRF_AZ_DRIVER_DW0_LBN … #define FRF_AZ_DRIVER_DW0_WIDTH … /* ALTERA_BUILD_REG: Altera build register */ #define FR_AZ_ALTERA_BUILD … #define FRF_AZ_ALTERA_BUILD_VER_LBN … #define FRF_AZ_ALTERA_BUILD_VER_WIDTH … /* CSR_SPARE_REG: Spare register */ #define FR_AZ_CSR_SPARE … #define FRF_AB_MEM_PERR_EN_LBN … #define FRF_AB_MEM_PERR_EN_WIDTH … #define FRF_CZ_MEM_PERR_EN_LBN … #define FRF_CZ_MEM_PERR_EN_WIDTH … #define FRF_AB_MEM_PERR_EN_TX_DATA_LBN … #define FRF_AB_MEM_PERR_EN_TX_DATA_WIDTH … #define FRF_AZ_CSR_SPARE_BITS_LBN … #define FRF_AZ_CSR_SPARE_BITS_WIDTH … /* PCIE_SD_CTL0123_REG: PCIE SerDes control register 0 to 3 */ #define FR_AB_PCIE_SD_CTL0123 … #define FRF_AB_PCIE_TESTSIG_H_LBN … #define FRF_AB_PCIE_TESTSIG_H_WIDTH … #define FRF_AB_PCIE_TESTSIG_L_LBN … #define FRF_AB_PCIE_TESTSIG_L_WIDTH … #define FRF_AB_PCIE_OFFSET_LBN … #define FRF_AB_PCIE_OFFSET_WIDTH … #define FRF_AB_PCIE_OFFSETEN_H_LBN … #define FRF_AB_PCIE_OFFSETEN_H_WIDTH … #define FRF_AB_PCIE_OFFSETEN_L_LBN … #define FRF_AB_PCIE_OFFSETEN_L_WIDTH … #define FRF_AB_PCIE_HIVMODE_H_LBN … #define FRF_AB_PCIE_HIVMODE_H_WIDTH … #define FRF_AB_PCIE_HIVMODE_L_LBN … #define FRF_AB_PCIE_HIVMODE_L_WIDTH … #define FRF_AB_PCIE_PARRESET_H_LBN … #define FRF_AB_PCIE_PARRESET_H_WIDTH … #define FRF_AB_PCIE_PARRESET_L_LBN … #define FRF_AB_PCIE_PARRESET_L_WIDTH … #define FRF_AB_PCIE_LPBKWDRV_H_LBN … #define FRF_AB_PCIE_LPBKWDRV_H_WIDTH … #define FRF_AB_PCIE_LPBKWDRV_L_LBN … #define FRF_AB_PCIE_LPBKWDRV_L_WIDTH … #define FRF_AB_PCIE_LPBK_LBN … #define FRF_AB_PCIE_LPBK_WIDTH … #define FRF_AB_PCIE_PARLPBK_LBN … #define FRF_AB_PCIE_PARLPBK_WIDTH … #define FRF_AB_PCIE_RXTERMADJ_H_LBN … #define FRF_AB_PCIE_RXTERMADJ_H_WIDTH … #define FRF_AB_PCIE_RXTERMADJ_L_LBN … #define FRF_AB_PCIE_RXTERMADJ_L_WIDTH … #define FFE_AB_PCIE_RXTERMADJ_MIN15PCNT … #define FFE_AB_PCIE_RXTERMADJ_PL10PCNT … #define FFE_AB_PCIE_RXTERMADJ_MIN17PCNT … #define FFE_AB_PCIE_RXTERMADJ_NOMNL … #define FRF_AB_PCIE_TXTERMADJ_H_LBN … #define FRF_AB_PCIE_TXTERMADJ_H_WIDTH … #define FRF_AB_PCIE_TXTERMADJ_L_LBN … #define FRF_AB_PCIE_TXTERMADJ_L_WIDTH … #define FFE_AB_PCIE_TXTERMADJ_MIN15PCNT … #define FFE_AB_PCIE_TXTERMADJ_PL10PCNT … #define FFE_AB_PCIE_TXTERMADJ_MIN17PCNT … #define FFE_AB_PCIE_TXTERMADJ_NOMNL … #define FRF_AB_PCIE_RXEQCTL_H_LBN … #define FRF_AB_PCIE_RXEQCTL_H_WIDTH … #define FRF_AB_PCIE_RXEQCTL_L_LBN … #define FRF_AB_PCIE_RXEQCTL_L_WIDTH … #define FFE_AB_PCIE_RXEQCTL_OFF_ALT … #define FFE_AB_PCIE_RXEQCTL_OFF … #define FFE_AB_PCIE_RXEQCTL_MIN … #define FFE_AB_PCIE_RXEQCTL_MAX … #define FRF_AB_PCIE_HIDRV_LBN … #define FRF_AB_PCIE_HIDRV_WIDTH … #define FRF_AB_PCIE_LODRV_LBN … #define FRF_AB_PCIE_LODRV_WIDTH … /* PCIE_SD_CTL45_REG: PCIE SerDes control register 4 and 5 */ #define FR_AB_PCIE_SD_CTL45 … #define FRF_AB_PCIE_DTX7_LBN … #define FRF_AB_PCIE_DTX7_WIDTH … #define FRF_AB_PCIE_DTX6_LBN … #define FRF_AB_PCIE_DTX6_WIDTH … #define FRF_AB_PCIE_DTX5_LBN … #define FRF_AB_PCIE_DTX5_WIDTH … #define FRF_AB_PCIE_DTX4_LBN … #define FRF_AB_PCIE_DTX4_WIDTH … #define FRF_AB_PCIE_DTX3_LBN … #define FRF_AB_PCIE_DTX3_WIDTH … #define FRF_AB_PCIE_DTX2_LBN … #define FRF_AB_PCIE_DTX2_WIDTH … #define FRF_AB_PCIE_DTX1_LBN … #define FRF_AB_PCIE_DTX1_WIDTH … #define FRF_AB_PCIE_DTX0_LBN … #define FRF_AB_PCIE_DTX0_WIDTH … #define FRF_AB_PCIE_DEQ7_LBN … #define FRF_AB_PCIE_DEQ7_WIDTH … #define FRF_AB_PCIE_DEQ6_LBN … #define FRF_AB_PCIE_DEQ6_WIDTH … #define FRF_AB_PCIE_DEQ5_LBN … #define FRF_AB_PCIE_DEQ5_WIDTH … #define FRF_AB_PCIE_DEQ4_LBN … #define FRF_AB_PCIE_DEQ4_WIDTH … #define FRF_AB_PCIE_DEQ3_LBN … #define FRF_AB_PCIE_DEQ3_WIDTH … #define FRF_AB_PCIE_DEQ2_LBN … #define FRF_AB_PCIE_DEQ2_WIDTH … #define FRF_AB_PCIE_DEQ1_LBN … #define FRF_AB_PCIE_DEQ1_WIDTH … #define FRF_AB_PCIE_DEQ0_LBN … #define FRF_AB_PCIE_DEQ0_WIDTH … /* PCIE_PCS_CTL_STAT_REG: PCIE PCS control and status register */ #define FR_AB_PCIE_PCS_CTL_STAT … #define FRF_AB_PCIE_PRBSERRCOUNT0_H_LBN … #define FRF_AB_PCIE_PRBSERRCOUNT0_H_WIDTH … #define FRF_AB_PCIE_PRBSERRCOUNT0_L_LBN … #define FRF_AB_PCIE_PRBSERRCOUNT0_L_WIDTH … #define FRF_AB_PCIE_PRBSERR_LBN … #define FRF_AB_PCIE_PRBSERR_WIDTH … #define FRF_AB_PCIE_PRBSERRH0_LBN … #define FRF_AB_PCIE_PRBSERRH0_WIDTH … #define FRF_AB_PCIE_FASTINIT_H_LBN … #define FRF_AB_PCIE_FASTINIT_H_WIDTH … #define FRF_AB_PCIE_FASTINIT_L_LBN … #define FRF_AB_PCIE_FASTINIT_L_WIDTH … #define FRF_AB_PCIE_CTCDISABLE_H_LBN … #define FRF_AB_PCIE_CTCDISABLE_H_WIDTH … #define FRF_AB_PCIE_CTCDISABLE_L_LBN … #define FRF_AB_PCIE_CTCDISABLE_L_WIDTH … #define FRF_AB_PCIE_PRBSSYNC_H_LBN … #define FRF_AB_PCIE_PRBSSYNC_H_WIDTH … #define FRF_AB_PCIE_PRBSSYNC_L_LBN … #define FRF_AB_PCIE_PRBSSYNC_L_WIDTH … #define FRF_AB_PCIE_PRBSERRACK_H_LBN … #define FRF_AB_PCIE_PRBSERRACK_H_WIDTH … #define FRF_AB_PCIE_PRBSERRACK_L_LBN … #define FRF_AB_PCIE_PRBSERRACK_L_WIDTH … #define FRF_AB_PCIE_PRBSSEL_LBN … #define FRF_AB_PCIE_PRBSSEL_WIDTH … /* DEBUG_DATA_OUT_REG: Live Debug and Debug 2 out ports */ #define FR_BB_DEBUG_DATA_OUT … #define FRF_BB_DEBUG2_PORT_LBN … #define FRF_BB_DEBUG2_PORT_WIDTH … #define FRF_BB_DEBUG1_PORT_LBN … #define FRF_BB_DEBUG1_PORT_WIDTH … /* EVQ_RPTR_REGP0: Event queue read pointer register */ #define FR_BZ_EVQ_RPTR_P0 … #define FR_BZ_EVQ_RPTR_P0_STEP … #define FR_BZ_EVQ_RPTR_P0_ROWS … /* EVQ_RPTR_REG_KER: Event queue read pointer register */ #define FR_AA_EVQ_RPTR_KER … #define FR_AA_EVQ_RPTR_KER_STEP … #define FR_AA_EVQ_RPTR_KER_ROWS … /* EVQ_RPTR_REG: Event queue read pointer register */ #define FR_BZ_EVQ_RPTR … #define FR_BZ_EVQ_RPTR_STEP … #define FR_BB_EVQ_RPTR_ROWS … #define FR_CZ_EVQ_RPTR_ROWS … /* EVQ_RPTR_REGP123: Event queue read pointer register */ #define FR_BB_EVQ_RPTR_P123 … #define FR_BB_EVQ_RPTR_P123_STEP … #define FR_BB_EVQ_RPTR_P123_ROWS … #define FRF_AZ_EVQ_RPTR_VLD_LBN … #define FRF_AZ_EVQ_RPTR_VLD_WIDTH … #define FRF_AZ_EVQ_RPTR_LBN … #define FRF_AZ_EVQ_RPTR_WIDTH … /* TIMER_COMMAND_REGP0: Timer Command Registers */ #define FR_BZ_TIMER_COMMAND_P0 … #define FR_BZ_TIMER_COMMAND_P0_STEP … #define FR_BZ_TIMER_COMMAND_P0_ROWS … /* TIMER_COMMAND_REG_KER: Timer Command Registers */ #define FR_AA_TIMER_COMMAND_KER … #define FR_AA_TIMER_COMMAND_KER_STEP … #define FR_AA_TIMER_COMMAND_KER_ROWS … /* TIMER_COMMAND_REGP123: Timer Command Registers */ #define FR_BB_TIMER_COMMAND_P123 … #define FR_BB_TIMER_COMMAND_P123_STEP … #define FR_BB_TIMER_COMMAND_P123_ROWS … #define FRF_CZ_TC_TIMER_MODE_LBN … #define FRF_CZ_TC_TIMER_MODE_WIDTH … #define FRF_AB_TC_TIMER_MODE_LBN … #define FRF_AB_TC_TIMER_MODE_WIDTH … #define FRF_CZ_TC_TIMER_VAL_LBN … #define FRF_CZ_TC_TIMER_VAL_WIDTH … #define FRF_AB_TC_TIMER_VAL_LBN … #define FRF_AB_TC_TIMER_VAL_WIDTH … /* DRV_EV_REG: Driver generated event register */ #define FR_AZ_DRV_EV … #define FRF_AZ_DRV_EV_QID_LBN … #define FRF_AZ_DRV_EV_QID_WIDTH … #define FRF_AZ_DRV_EV_DATA_LBN … #define FRF_AZ_DRV_EV_DATA_WIDTH … /* EVQ_CTL_REG: Event queue control register */ #define FR_AZ_EVQ_CTL … #define FRF_CZ_RX_EVQ_WAKEUP_MASK_LBN … #define FRF_CZ_RX_EVQ_WAKEUP_MASK_WIDTH … #define FRF_BB_RX_EVQ_WAKEUP_MASK_LBN … #define FRF_BB_RX_EVQ_WAKEUP_MASK_WIDTH … #define FRF_AZ_EVQ_OWNERR_CTL_LBN … #define FRF_AZ_EVQ_OWNERR_CTL_WIDTH … #define FRF_AZ_EVQ_FIFO_AF_TH_LBN … #define FRF_AZ_EVQ_FIFO_AF_TH_WIDTH … #define FRF_AZ_EVQ_FIFO_NOTAF_TH_LBN … #define FRF_AZ_EVQ_FIFO_NOTAF_TH_WIDTH … /* EVQ_CNT1_REG: Event counter 1 register */ #define FR_AZ_EVQ_CNT1 … #define FRF_AZ_EVQ_CNT_PRE_FIFO_LBN … #define FRF_AZ_EVQ_CNT_PRE_FIFO_WIDTH … #define FRF_AZ_EVQ_CNT_TOBIU_LBN … #define FRF_AZ_EVQ_CNT_TOBIU_WIDTH … #define FRF_AZ_EVQ_TX_REQ_CNT_LBN … #define FRF_AZ_EVQ_TX_REQ_CNT_WIDTH … #define FRF_AZ_EVQ_RX_REQ_CNT_LBN … #define FRF_AZ_EVQ_RX_REQ_CNT_WIDTH … #define FRF_AZ_EVQ_EM_REQ_CNT_LBN … #define FRF_AZ_EVQ_EM_REQ_CNT_WIDTH … #define FRF_AZ_EVQ_CSR_REQ_CNT_LBN … #define FRF_AZ_EVQ_CSR_REQ_CNT_WIDTH … #define FRF_AZ_EVQ_ERR_REQ_CNT_LBN … #define FRF_AZ_EVQ_ERR_REQ_CNT_WIDTH … /* EVQ_CNT2_REG: Event counter 2 register */ #define FR_AZ_EVQ_CNT2 … #define FRF_AZ_EVQ_UPD_REQ_CNT_LBN … #define FRF_AZ_EVQ_UPD_REQ_CNT_WIDTH … #define FRF_AZ_EVQ_CLR_REQ_CNT_LBN … #define FRF_AZ_EVQ_CLR_REQ_CNT_WIDTH … #define FRF_AZ_EVQ_RDY_CNT_LBN … #define FRF_AZ_EVQ_RDY_CNT_WIDTH … #define FRF_AZ_EVQ_WU_REQ_CNT_LBN … #define FRF_AZ_EVQ_WU_REQ_CNT_WIDTH … #define FRF_AZ_EVQ_WET_REQ_CNT_LBN … #define FRF_AZ_EVQ_WET_REQ_CNT_WIDTH … #define FRF_AZ_EVQ_INIT_REQ_CNT_LBN … #define FRF_AZ_EVQ_INIT_REQ_CNT_WIDTH … #define FRF_AZ_EVQ_TM_REQ_CNT_LBN … #define FRF_AZ_EVQ_TM_REQ_CNT_WIDTH … /* USR_EV_REG: Event mailbox register */ #define FR_CZ_USR_EV … #define FR_CZ_USR_EV_STEP … #define FR_CZ_USR_EV_ROWS … #define FRF_CZ_USR_EV_DATA_LBN … #define FRF_CZ_USR_EV_DATA_WIDTH … /* BUF_TBL_CFG_REG: Buffer table configuration register */ #define FR_AZ_BUF_TBL_CFG … #define FRF_AZ_BUF_TBL_MODE_LBN … #define FRF_AZ_BUF_TBL_MODE_WIDTH … /* SRM_RX_DC_CFG_REG: SRAM receive descriptor cache configuration register */ #define FR_AZ_SRM_RX_DC_CFG … #define FRF_AZ_SRM_CLK_TMP_EN_LBN … #define FRF_AZ_SRM_CLK_TMP_EN_WIDTH … #define FRF_AZ_SRM_RX_DC_BASE_ADR_LBN … #define FRF_AZ_SRM_RX_DC_BASE_ADR_WIDTH … /* SRM_TX_DC_CFG_REG: SRAM transmit descriptor cache configuration register */ #define FR_AZ_SRM_TX_DC_CFG … #define FRF_AZ_SRM_TX_DC_BASE_ADR_LBN … #define FRF_AZ_SRM_TX_DC_BASE_ADR_WIDTH … /* SRM_CFG_REG: SRAM configuration register */ #define FR_AZ_SRM_CFG … #define FRF_AZ_SRM_OOB_ADR_INTEN_LBN … #define FRF_AZ_SRM_OOB_ADR_INTEN_WIDTH … #define FRF_AZ_SRM_OOB_BUF_INTEN_LBN … #define FRF_AZ_SRM_OOB_BUF_INTEN_WIDTH … #define FRF_AZ_SRM_INIT_EN_LBN … #define FRF_AZ_SRM_INIT_EN_WIDTH … #define FRF_AZ_SRM_NUM_BANK_LBN … #define FRF_AZ_SRM_NUM_BANK_WIDTH … #define FRF_AZ_SRM_BANK_SIZE_LBN … #define FRF_AZ_SRM_BANK_SIZE_WIDTH … /* BUF_TBL_UPD_REG: Buffer table update register */ #define FR_AZ_BUF_TBL_UPD … #define FRF_AZ_BUF_UPD_CMD_LBN … #define FRF_AZ_BUF_UPD_CMD_WIDTH … #define FRF_AZ_BUF_CLR_CMD_LBN … #define FRF_AZ_BUF_CLR_CMD_WIDTH … #define FRF_AZ_BUF_CLR_END_ID_LBN … #define FRF_AZ_BUF_CLR_END_ID_WIDTH … #define FRF_AZ_BUF_CLR_START_ID_LBN … #define FRF_AZ_BUF_CLR_START_ID_WIDTH … /* SRM_UPD_EVQ_REG: Buffer table update register */ #define FR_AZ_SRM_UPD_EVQ … #define FRF_AZ_SRM_UPD_EVQ_ID_LBN … #define FRF_AZ_SRM_UPD_EVQ_ID_WIDTH … /* SRAM_PARITY_REG: SRAM parity register. */ #define FR_AZ_SRAM_PARITY … #define FRF_CZ_BYPASS_ECC_LBN … #define FRF_CZ_BYPASS_ECC_WIDTH … #define FRF_CZ_SEC_INT_LBN … #define FRF_CZ_SEC_INT_WIDTH … #define FRF_CZ_FORCE_SRAM_DOUBLE_ERR_LBN … #define FRF_CZ_FORCE_SRAM_DOUBLE_ERR_WIDTH … #define FRF_AB_FORCE_SRAM_PERR_LBN … #define FRF_AB_FORCE_SRAM_PERR_WIDTH … #define FRF_CZ_FORCE_SRAM_SINGLE_ERR_LBN … #define FRF_CZ_FORCE_SRAM_SINGLE_ERR_WIDTH … /* RX_CFG_REG: Receive configuration register */ #define FR_AZ_RX_CFG … #define FRF_CZ_RX_MIN_KBUF_SIZE_LBN … #define FRF_CZ_RX_MIN_KBUF_SIZE_WIDTH … #define FRF_CZ_RX_HDR_SPLIT_EN_LBN … #define FRF_CZ_RX_HDR_SPLIT_EN_WIDTH … #define FRF_CZ_RX_HDR_SPLIT_PLD_BUF_SIZE_LBN … #define FRF_CZ_RX_HDR_SPLIT_PLD_BUF_SIZE_WIDTH … #define FRF_CZ_RX_HDR_SPLIT_HDR_BUF_SIZE_LBN … #define FRF_CZ_RX_HDR_SPLIT_HDR_BUF_SIZE_WIDTH … #define FRF_CZ_RX_PRE_RFF_IPG_LBN … #define FRF_CZ_RX_PRE_RFF_IPG_WIDTH … #define FRF_BZ_RX_TCP_SUP_LBN … #define FRF_BZ_RX_TCP_SUP_WIDTH … #define FRF_BZ_RX_INGR_EN_LBN … #define FRF_BZ_RX_INGR_EN_WIDTH … #define FRF_BZ_RX_IP_HASH_LBN … #define FRF_BZ_RX_IP_HASH_WIDTH … #define FRF_BZ_RX_HASH_ALG_LBN … #define FRF_BZ_RX_HASH_ALG_WIDTH … #define FRF_BZ_RX_HASH_INSRT_HDR_LBN … #define FRF_BZ_RX_HASH_INSRT_HDR_WIDTH … #define FRF_BZ_RX_DESC_PUSH_EN_LBN … #define FRF_BZ_RX_DESC_PUSH_EN_WIDTH … #define FRF_BZ_RX_RDW_PATCH_EN_LBN … #define FRF_BZ_RX_RDW_PATCH_EN_WIDTH … #define FRF_BB_RX_PCI_BURST_SIZE_LBN … #define FRF_BB_RX_PCI_BURST_SIZE_WIDTH … #define FRF_BZ_RX_OWNERR_CTL_LBN … #define FRF_BZ_RX_OWNERR_CTL_WIDTH … #define FRF_BZ_RX_XON_TX_TH_LBN … #define FRF_BZ_RX_XON_TX_TH_WIDTH … #define FRF_AA_RX_DESC_PUSH_EN_LBN … #define FRF_AA_RX_DESC_PUSH_EN_WIDTH … #define FRF_AA_RX_RDW_PATCH_EN_LBN … #define FRF_AA_RX_RDW_PATCH_EN_WIDTH … #define FRF_AA_RX_PCI_BURST_SIZE_LBN … #define FRF_AA_RX_PCI_BURST_SIZE_WIDTH … #define FRF_BZ_RX_XOFF_TX_TH_LBN … #define FRF_BZ_RX_XOFF_TX_TH_WIDTH … #define FRF_AA_RX_OWNERR_CTL_LBN … #define FRF_AA_RX_OWNERR_CTL_WIDTH … #define FRF_AA_RX_XON_TX_TH_LBN … #define FRF_AA_RX_XON_TX_TH_WIDTH … #define FRF_BZ_RX_USR_BUF_SIZE_LBN … #define FRF_BZ_RX_USR_BUF_SIZE_WIDTH … #define FRF_AA_RX_XOFF_TX_TH_LBN … #define FRF_AA_RX_XOFF_TX_TH_WIDTH … #define FRF_AA_RX_USR_BUF_SIZE_LBN … #define FRF_AA_RX_USR_BUF_SIZE_WIDTH … #define FRF_BZ_RX_XON_MAC_TH_LBN … #define FRF_BZ_RX_XON_MAC_TH_WIDTH … #define FRF_AA_RX_XON_MAC_TH_LBN … #define FRF_AA_RX_XON_MAC_TH_WIDTH … #define FRF_BZ_RX_XOFF_MAC_TH_LBN … #define FRF_BZ_RX_XOFF_MAC_TH_WIDTH … #define FRF_AA_RX_XOFF_MAC_TH_LBN … #define FRF_AA_RX_XOFF_MAC_TH_WIDTH … #define FRF_AZ_RX_XOFF_MAC_EN_LBN … #define FRF_AZ_RX_XOFF_MAC_EN_WIDTH … /* RX_FILTER_CTL_REG: Receive filter control registers */ #define FR_BZ_RX_FILTER_CTL … #define FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT_LBN … #define FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT_WIDTH … #define FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT_LBN … #define FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT_WIDTH … #define FRF_CZ_RX_FILTER_ALL_VLAN_ETHERTYPES_LBN … #define FRF_CZ_RX_FILTER_ALL_VLAN_ETHERTYPES_WIDTH … #define FRF_CZ_RX_VLAN_MATCH_ETHERTYPE_LBN … #define FRF_CZ_RX_VLAN_MATCH_ETHERTYPE_WIDTH … #define FRF_CZ_MULTICAST_NOMATCH_Q_ID_LBN … #define FRF_CZ_MULTICAST_NOMATCH_Q_ID_WIDTH … #define FRF_CZ_MULTICAST_NOMATCH_RSS_ENABLED_LBN … #define FRF_CZ_MULTICAST_NOMATCH_RSS_ENABLED_WIDTH … #define FRF_CZ_MULTICAST_NOMATCH_IP_OVERRIDE_LBN … #define FRF_CZ_MULTICAST_NOMATCH_IP_OVERRIDE_WIDTH … #define FRF_CZ_UNICAST_NOMATCH_Q_ID_LBN … #define FRF_CZ_UNICAST_NOMATCH_Q_ID_WIDTH … #define FRF_CZ_UNICAST_NOMATCH_RSS_ENABLED_LBN … #define FRF_CZ_UNICAST_NOMATCH_RSS_ENABLED_WIDTH … #define FRF_CZ_UNICAST_NOMATCH_IP_OVERRIDE_LBN … #define FRF_CZ_UNICAST_NOMATCH_IP_OVERRIDE_WIDTH … #define FRF_BZ_SCATTER_ENBL_NO_MATCH_Q_LBN … #define FRF_BZ_SCATTER_ENBL_NO_MATCH_Q_WIDTH … #define FRF_BZ_UDP_FULL_SRCH_LIMIT_LBN … #define FRF_BZ_UDP_FULL_SRCH_LIMIT_WIDTH … #define FRF_BZ_NUM_KER_LBN … #define FRF_BZ_NUM_KER_WIDTH … #define FRF_BZ_UDP_WILD_SRCH_LIMIT_LBN … #define FRF_BZ_UDP_WILD_SRCH_LIMIT_WIDTH … #define FRF_BZ_TCP_WILD_SRCH_LIMIT_LBN … #define FRF_BZ_TCP_WILD_SRCH_LIMIT_WIDTH … #define FRF_BZ_TCP_FULL_SRCH_LIMIT_LBN … #define FRF_BZ_TCP_FULL_SRCH_LIMIT_WIDTH … /* RX_FLUSH_DESCQ_REG: Receive flush descriptor queue register */ #define FR_AZ_RX_FLUSH_DESCQ … #define FRF_AZ_RX_FLUSH_DESCQ_CMD_LBN … #define FRF_AZ_RX_FLUSH_DESCQ_CMD_WIDTH … #define FRF_AZ_RX_FLUSH_DESCQ_LBN … #define FRF_AZ_RX_FLUSH_DESCQ_WIDTH … /* RX_DESC_UPD_REGP0: Receive descriptor update register. */ #define FR_BZ_RX_DESC_UPD_P0 … #define FR_BZ_RX_DESC_UPD_P0_STEP … #define FR_BZ_RX_DESC_UPD_P0_ROWS … /* RX_DESC_UPD_REG_KER: Receive descriptor update register. */ #define FR_AA_RX_DESC_UPD_KER … #define FR_AA_RX_DESC_UPD_KER_STEP … #define FR_AA_RX_DESC_UPD_KER_ROWS … /* RX_DESC_UPD_REGP123: Receive descriptor update register. */ #define FR_BB_RX_DESC_UPD_P123 … #define FR_BB_RX_DESC_UPD_P123_STEP … #define FR_BB_RX_DESC_UPD_P123_ROWS … #define FRF_AZ_RX_DESC_WPTR_LBN … #define FRF_AZ_RX_DESC_WPTR_WIDTH … #define FRF_AZ_RX_DESC_PUSH_CMD_LBN … #define FRF_AZ_RX_DESC_PUSH_CMD_WIDTH … #define FRF_AZ_RX_DESC_LBN … #define FRF_AZ_RX_DESC_WIDTH … /* RX_DC_CFG_REG: Receive descriptor cache configuration register */ #define FR_AZ_RX_DC_CFG … #define FRF_AB_RX_MAX_PF_LBN … #define FRF_AB_RX_MAX_PF_WIDTH … #define FRF_AZ_RX_DC_SIZE_LBN … #define FRF_AZ_RX_DC_SIZE_WIDTH … #define FFE_AZ_RX_DC_SIZE_64 … #define FFE_AZ_RX_DC_SIZE_32 … #define FFE_AZ_RX_DC_SIZE_16 … #define FFE_AZ_RX_DC_SIZE_8 … /* RX_DC_PF_WM_REG: Receive descriptor cache pre-fetch watermark register */ #define FR_AZ_RX_DC_PF_WM … #define FRF_AZ_RX_DC_PF_HWM_LBN … #define FRF_AZ_RX_DC_PF_HWM_WIDTH … #define FRF_AZ_RX_DC_PF_LWM_LBN … #define FRF_AZ_RX_DC_PF_LWM_WIDTH … /* RX_RSS_TKEY_REG: RSS Toeplitz hash key */ #define FR_BZ_RX_RSS_TKEY … #define FRF_BZ_RX_RSS_TKEY_HI_LBN … #define FRF_BZ_RX_RSS_TKEY_HI_WIDTH … #define FRF_BZ_RX_RSS_TKEY_LO_LBN … #define FRF_BZ_RX_RSS_TKEY_LO_WIDTH … /* RX_NODESC_DROP_REG: Receive dropped packet counter register */ #define FR_AZ_RX_NODESC_DROP … #define FRF_CZ_RX_NODESC_DROP_CNT_LBN … #define FRF_CZ_RX_NODESC_DROP_CNT_WIDTH … #define FRF_AB_RX_NODESC_DROP_CNT_LBN … #define FRF_AB_RX_NODESC_DROP_CNT_WIDTH … /* RX_SELF_RST_REG: Receive self reset register */ #define FR_AA_RX_SELF_RST … #define FRF_AA_RX_ISCSI_DIS_LBN … #define FRF_AA_RX_ISCSI_DIS_WIDTH … #define FRF_AA_RX_SW_RST_REG_LBN … #define FRF_AA_RX_SW_RST_REG_WIDTH … #define FRF_AA_RX_NODESC_WAIT_DIS_LBN … #define FRF_AA_RX_NODESC_WAIT_DIS_WIDTH … #define FRF_AA_RX_SELF_RST_EN_LBN … #define FRF_AA_RX_SELF_RST_EN_WIDTH … #define FRF_AA_RX_MAX_PF_LAT_LBN … #define FRF_AA_RX_MAX_PF_LAT_WIDTH … #define FRF_AA_RX_MAX_LU_LAT_LBN … #define FRF_AA_RX_MAX_LU_LAT_WIDTH … /* RX_DEBUG_REG: undocumented register */ #define FR_AZ_RX_DEBUG … #define FRF_AZ_RX_DEBUG_LBN … #define FRF_AZ_RX_DEBUG_WIDTH … /* RX_PUSH_DROP_REG: Receive descriptor push dropped counter register */ #define FR_AZ_RX_PUSH_DROP … #define FRF_AZ_RX_PUSH_DROP_CNT_LBN … #define FRF_AZ_RX_PUSH_DROP_CNT_WIDTH … /* RX_RSS_IPV6_REG1: IPv6 RSS Toeplitz hash key low bytes */ #define FR_CZ_RX_RSS_IPV6_REG1 … #define FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN … #define FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH … /* RX_RSS_IPV6_REG2: IPv6 RSS Toeplitz hash key middle bytes */ #define FR_CZ_RX_RSS_IPV6_REG2 … #define FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN … #define FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH … /* RX_RSS_IPV6_REG3: IPv6 RSS Toeplitz hash key upper bytes and IPv6 RSS settings */ #define FR_CZ_RX_RSS_IPV6_REG3 … #define FRF_CZ_RX_RSS_IPV6_THASH_ENABLE_LBN … #define FRF_CZ_RX_RSS_IPV6_THASH_ENABLE_WIDTH … #define FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE_LBN … #define FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE_WIDTH … #define FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS_LBN … #define FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS_WIDTH … #define FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN … #define FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH … /* TX_FLUSH_DESCQ_REG: Transmit flush descriptor queue register */ #define FR_AZ_TX_FLUSH_DESCQ … #define FRF_AZ_TX_FLUSH_DESCQ_CMD_LBN … #define FRF_AZ_TX_FLUSH_DESCQ_CMD_WIDTH … #define FRF_AZ_TX_FLUSH_DESCQ_LBN … #define FRF_AZ_TX_FLUSH_DESCQ_WIDTH … /* TX_DESC_UPD_REGP0: Transmit descriptor update register. */ #define FR_BZ_TX_DESC_UPD_P0 … #define FR_BZ_TX_DESC_UPD_P0_STEP … #define FR_BZ_TX_DESC_UPD_P0_ROWS … /* TX_DESC_UPD_REG_KER: Transmit descriptor update register. */ #define FR_AA_TX_DESC_UPD_KER … #define FR_AA_TX_DESC_UPD_KER_STEP … #define FR_AA_TX_DESC_UPD_KER_ROWS … /* TX_DESC_UPD_REGP123: Transmit descriptor update register. */ #define FR_BB_TX_DESC_UPD_P123 … #define FR_BB_TX_DESC_UPD_P123_STEP … #define FR_BB_TX_DESC_UPD_P123_ROWS … #define FRF_AZ_TX_DESC_WPTR_LBN … #define FRF_AZ_TX_DESC_WPTR_WIDTH … #define FRF_AZ_TX_DESC_PUSH_CMD_LBN … #define FRF_AZ_TX_DESC_PUSH_CMD_WIDTH … #define FRF_AZ_TX_DESC_LBN … #define FRF_AZ_TX_DESC_WIDTH … /* TX_DC_CFG_REG: Transmit descriptor cache configuration register */ #define FR_AZ_TX_DC_CFG … #define FRF_AZ_TX_DC_SIZE_LBN … #define FRF_AZ_TX_DC_SIZE_WIDTH … #define FFE_AZ_TX_DC_SIZE_32 … #define FFE_AZ_TX_DC_SIZE_16 … #define FFE_AZ_TX_DC_SIZE_8 … /* TX_CHKSM_CFG_REG: Transmit checksum configuration register */ #define FR_AA_TX_CHKSM_CFG … #define FRF_AA_TX_Q_CHKSM_DIS_96_127_LBN … #define FRF_AA_TX_Q_CHKSM_DIS_96_127_WIDTH … #define FRF_AA_TX_Q_CHKSM_DIS_64_95_LBN … #define FRF_AA_TX_Q_CHKSM_DIS_64_95_WIDTH … #define FRF_AA_TX_Q_CHKSM_DIS_32_63_LBN … #define FRF_AA_TX_Q_CHKSM_DIS_32_63_WIDTH … #define FRF_AA_TX_Q_CHKSM_DIS_0_31_LBN … #define FRF_AA_TX_Q_CHKSM_DIS_0_31_WIDTH … /* TX_CFG_REG: Transmit configuration register */ #define FR_AZ_TX_CFG … #define FRF_CZ_TX_CONT_LOOKUP_THRESH_RANGE_LBN … #define FRF_CZ_TX_CONT_LOOKUP_THRESH_RANGE_WIDTH … #define FRF_CZ_TX_FILTER_TEST_MODE_BIT_LBN … #define FRF_CZ_TX_FILTER_TEST_MODE_BIT_WIDTH … #define FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE_LBN … #define FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE_WIDTH … #define FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE_LBN … #define FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE_WIDTH … #define FRF_CZ_TX_UDPIP_FILTER_WILD_SEARCH_RANGE_LBN … #define FRF_CZ_TX_UDPIP_FILTER_WILD_SEARCH_RANGE_WIDTH … #define FRF_CZ_TX_UDPIP_FILTER_FULL_SEARCH_RANGE_LBN … #define FRF_CZ_TX_UDPIP_FILTER_FULL_SEARCH_RANGE_WIDTH … #define FRF_CZ_TX_TCPIP_FILTER_WILD_SEARCH_RANGE_LBN … #define FRF_CZ_TX_TCPIP_FILTER_WILD_SEARCH_RANGE_WIDTH … #define FRF_CZ_TX_TCPIP_FILTER_FULL_SEARCH_RANGE_LBN … #define FRF_CZ_TX_TCPIP_FILTER_FULL_SEARCH_RANGE_WIDTH … #define FRF_CZ_TX_FILTER_ALL_VLAN_ETHERTYPES_BIT_LBN … #define FRF_CZ_TX_FILTER_ALL_VLAN_ETHERTYPES_BIT_WIDTH … #define FRF_CZ_TX_VLAN_MATCH_ETHERTYPE_RANGE_LBN … #define FRF_CZ_TX_VLAN_MATCH_ETHERTYPE_RANGE_WIDTH … #define FRF_CZ_TX_FILTER_EN_BIT_LBN … #define FRF_CZ_TX_FILTER_EN_BIT_WIDTH … #define FRF_AZ_TX_IP_ID_P0_OFS_LBN … #define FRF_AZ_TX_IP_ID_P0_OFS_WIDTH … #define FRF_AZ_TX_NO_EOP_DISC_EN_LBN … #define FRF_AZ_TX_NO_EOP_DISC_EN_WIDTH … #define FRF_AZ_TX_P1_PRI_EN_LBN … #define FRF_AZ_TX_P1_PRI_EN_WIDTH … #define FRF_AZ_TX_OWNERR_CTL_LBN … #define FRF_AZ_TX_OWNERR_CTL_WIDTH … #define FRF_AA_TX_NON_IP_DROP_DIS_LBN … #define FRF_AA_TX_NON_IP_DROP_DIS_WIDTH … #define FRF_AZ_TX_IP_ID_REP_EN_LBN … #define FRF_AZ_TX_IP_ID_REP_EN_WIDTH … /* TX_PUSH_DROP_REG: Transmit push dropped register */ #define FR_AZ_TX_PUSH_DROP … #define FRF_AZ_TX_PUSH_DROP_CNT_LBN … #define FRF_AZ_TX_PUSH_DROP_CNT_WIDTH … /* TX_RESERVED_REG: Transmit configuration register */ #define FR_AZ_TX_RESERVED … #define FRF_AZ_TX_EVT_CNT_LBN … #define FRF_AZ_TX_EVT_CNT_WIDTH … #define FRF_AZ_TX_PREF_AGE_CNT_LBN … #define FRF_AZ_TX_PREF_AGE_CNT_WIDTH … #define FRF_AZ_TX_RD_COMP_TMR_LBN … #define FRF_AZ_TX_RD_COMP_TMR_WIDTH … #define FRF_AZ_TX_PUSH_EN_LBN … #define FRF_AZ_TX_PUSH_EN_WIDTH … #define FRF_AZ_TX_PUSH_CHK_DIS_LBN … #define FRF_AZ_TX_PUSH_CHK_DIS_WIDTH … #define FRF_AZ_TX_D_FF_FULL_P0_LBN … #define FRF_AZ_TX_D_FF_FULL_P0_WIDTH … #define FRF_AZ_TX_DMAR_ST_P0_LBN … #define FRF_AZ_TX_DMAR_ST_P0_WIDTH … #define FRF_AZ_TX_DMAQ_ST_LBN … #define FRF_AZ_TX_DMAQ_ST_WIDTH … #define FRF_AZ_TX_RX_SPACER_LBN … #define FRF_AZ_TX_RX_SPACER_WIDTH … #define FRF_AZ_TX_DROP_ABORT_EN_LBN … #define FRF_AZ_TX_DROP_ABORT_EN_WIDTH … #define FRF_AZ_TX_SOFT_EVT_EN_LBN … #define FRF_AZ_TX_SOFT_EVT_EN_WIDTH … #define FRF_AZ_TX_PS_EVT_DIS_LBN … #define FRF_AZ_TX_PS_EVT_DIS_WIDTH … #define FRF_AZ_TX_RX_SPACER_EN_LBN … #define FRF_AZ_TX_RX_SPACER_EN_WIDTH … #define FRF_AZ_TX_XP_TIMER_LBN … #define FRF_AZ_TX_XP_TIMER_WIDTH … #define FRF_AZ_TX_PREF_SPACER_LBN … #define FRF_AZ_TX_PREF_SPACER_WIDTH … #define FRF_AZ_TX_PREF_WD_TMR_LBN … #define FRF_AZ_TX_PREF_WD_TMR_WIDTH … #define FRF_AZ_TX_ONLY1TAG_LBN … #define FRF_AZ_TX_ONLY1TAG_WIDTH … #define FRF_AZ_TX_PREF_THRESHOLD_LBN … #define FRF_AZ_TX_PREF_THRESHOLD_WIDTH … #define FRF_AZ_TX_ONE_PKT_PER_Q_LBN … #define FRF_AZ_TX_ONE_PKT_PER_Q_WIDTH … #define FRF_AZ_TX_DIS_NON_IP_EV_LBN … #define FRF_AZ_TX_DIS_NON_IP_EV_WIDTH … #define FRF_AA_TX_DMA_FF_THR_LBN … #define FRF_AA_TX_DMA_FF_THR_WIDTH … #define FRF_AZ_TX_DMA_SPACER_LBN … #define FRF_AZ_TX_DMA_SPACER_WIDTH … #define FRF_AA_TX_TCP_DIS_LBN … #define FRF_AA_TX_TCP_DIS_WIDTH … #define FRF_BZ_TX_FLUSH_MIN_LEN_EN_LBN … #define FRF_BZ_TX_FLUSH_MIN_LEN_EN_WIDTH … #define FRF_AA_TX_IP_DIS_LBN … #define FRF_AA_TX_IP_DIS_WIDTH … #define FRF_AZ_TX_MAX_CPL_LBN … #define FRF_AZ_TX_MAX_CPL_WIDTH … #define FFE_AZ_TX_MAX_CPL_16 … #define FFE_AZ_TX_MAX_CPL_8 … #define FFE_AZ_TX_MAX_CPL_4 … #define FFE_AZ_TX_MAX_CPL_NOLIMIT … #define FRF_AZ_TX_MAX_PREF_LBN … #define FRF_AZ_TX_MAX_PREF_WIDTH … #define FFE_AZ_TX_MAX_PREF_32 … #define FFE_AZ_TX_MAX_PREF_16 … #define FFE_AZ_TX_MAX_PREF_8 … #define FFE_AZ_TX_MAX_PREF_OFF … /* TX_PACE_REG: Transmit pace control register */ #define FR_BZ_TX_PACE … #define FRF_BZ_TX_PACE_SB_NOT_AF_LBN … #define FRF_BZ_TX_PACE_SB_NOT_AF_WIDTH … #define FRF_BZ_TX_PACE_SB_AF_LBN … #define FRF_BZ_TX_PACE_SB_AF_WIDTH … #define FRF_BZ_TX_PACE_FB_BASE_LBN … #define FRF_BZ_TX_PACE_FB_BASE_WIDTH … #define FRF_BZ_TX_PACE_BIN_TH_LBN … #define FRF_BZ_TX_PACE_BIN_TH_WIDTH … /* TX_PACE_DROP_QID_REG: PACE Drop QID Counter */ #define FR_BZ_TX_PACE_DROP_QID … #define FRF_BZ_TX_PACE_QID_DRP_CNT_LBN … #define FRF_BZ_TX_PACE_QID_DRP_CNT_WIDTH … /* TX_VLAN_REG: Transmit VLAN tag register */ #define FR_BB_TX_VLAN … #define FRF_BB_TX_VLAN_EN_LBN … #define FRF_BB_TX_VLAN_EN_WIDTH … #define FRF_BB_TX_VLAN7_PORT1_EN_LBN … #define FRF_BB_TX_VLAN7_PORT1_EN_WIDTH … #define FRF_BB_TX_VLAN7_PORT0_EN_LBN … #define FRF_BB_TX_VLAN7_PORT0_EN_WIDTH … #define FRF_BB_TX_VLAN7_LBN … #define FRF_BB_TX_VLAN7_WIDTH … #define FRF_BB_TX_VLAN6_PORT1_EN_LBN … #define FRF_BB_TX_VLAN6_PORT1_EN_WIDTH … #define FRF_BB_TX_VLAN6_PORT0_EN_LBN … #define FRF_BB_TX_VLAN6_PORT0_EN_WIDTH … #define FRF_BB_TX_VLAN6_LBN … #define FRF_BB_TX_VLAN6_WIDTH … #define FRF_BB_TX_VLAN5_PORT1_EN_LBN … #define FRF_BB_TX_VLAN5_PORT1_EN_WIDTH … #define FRF_BB_TX_VLAN5_PORT0_EN_LBN … #define FRF_BB_TX_VLAN5_PORT0_EN_WIDTH … #define FRF_BB_TX_VLAN5_LBN … #define FRF_BB_TX_VLAN5_WIDTH … #define FRF_BB_TX_VLAN4_PORT1_EN_LBN … #define FRF_BB_TX_VLAN4_PORT1_EN_WIDTH … #define FRF_BB_TX_VLAN4_PORT0_EN_LBN … #define FRF_BB_TX_VLAN4_PORT0_EN_WIDTH … #define FRF_BB_TX_VLAN4_LBN … #define FRF_BB_TX_VLAN4_WIDTH … #define FRF_BB_TX_VLAN3_PORT1_EN_LBN … #define FRF_BB_TX_VLAN3_PORT1_EN_WIDTH … #define FRF_BB_TX_VLAN3_PORT0_EN_LBN … #define FRF_BB_TX_VLAN3_PORT0_EN_WIDTH … #define FRF_BB_TX_VLAN3_LBN … #define FRF_BB_TX_VLAN3_WIDTH … #define FRF_BB_TX_VLAN2_PORT1_EN_LBN … #define FRF_BB_TX_VLAN2_PORT1_EN_WIDTH … #define FRF_BB_TX_VLAN2_PORT0_EN_LBN … #define FRF_BB_TX_VLAN2_PORT0_EN_WIDTH … #define FRF_BB_TX_VLAN2_LBN … #define FRF_BB_TX_VLAN2_WIDTH … #define FRF_BB_TX_VLAN1_PORT1_EN_LBN … #define FRF_BB_TX_VLAN1_PORT1_EN_WIDTH … #define FRF_BB_TX_VLAN1_PORT0_EN_LBN … #define FRF_BB_TX_VLAN1_PORT0_EN_WIDTH … #define FRF_BB_TX_VLAN1_LBN … #define FRF_BB_TX_VLAN1_WIDTH … #define FRF_BB_TX_VLAN0_PORT1_EN_LBN … #define FRF_BB_TX_VLAN0_PORT1_EN_WIDTH … #define FRF_BB_TX_VLAN0_PORT0_EN_LBN … #define FRF_BB_TX_VLAN0_PORT0_EN_WIDTH … #define FRF_BB_TX_VLAN0_LBN … #define FRF_BB_TX_VLAN0_WIDTH … /* TX_IPFIL_PORTEN_REG: Transmit filter control register */ #define FR_BZ_TX_IPFIL_PORTEN … #define FRF_BZ_TX_MADR0_FIL_EN_LBN … #define FRF_BZ_TX_MADR0_FIL_EN_WIDTH … #define FRF_BB_TX_IPFIL31_PORT_EN_LBN … #define FRF_BB_TX_IPFIL31_PORT_EN_WIDTH … #define FRF_BB_TX_IPFIL30_PORT_EN_LBN … #define FRF_BB_TX_IPFIL30_PORT_EN_WIDTH … #define FRF_BB_TX_IPFIL29_PORT_EN_LBN … #define FRF_BB_TX_IPFIL29_PORT_EN_WIDTH … #define FRF_BB_TX_IPFIL28_PORT_EN_LBN … #define FRF_BB_TX_IPFIL28_PORT_EN_WIDTH … #define FRF_BB_TX_IPFIL27_PORT_EN_LBN … #define FRF_BB_TX_IPFIL27_PORT_EN_WIDTH … #define FRF_BB_TX_IPFIL26_PORT_EN_LBN … #define FRF_BB_TX_IPFIL26_PORT_EN_WIDTH … #define FRF_BB_TX_IPFIL25_PORT_EN_LBN … #define FRF_BB_TX_IPFIL25_PORT_EN_WIDTH … #define FRF_BB_TX_IPFIL24_PORT_EN_LBN … #define FRF_BB_TX_IPFIL24_PORT_EN_WIDTH … #define FRF_BB_TX_IPFIL23_PORT_EN_LBN … #define FRF_BB_TX_IPFIL23_PORT_EN_WIDTH … #define FRF_BB_TX_IPFIL22_PORT_EN_LBN … #define FRF_BB_TX_IPFIL22_PORT_EN_WIDTH … #define FRF_BB_TX_IPFIL21_PORT_EN_LBN … #define FRF_BB_TX_IPFIL21_PORT_EN_WIDTH … #define FRF_BB_TX_IPFIL20_PORT_EN_LBN … #define FRF_BB_TX_IPFIL20_PORT_EN_WIDTH … #define FRF_BB_TX_IPFIL19_PORT_EN_LBN … #define FRF_BB_TX_IPFIL19_PORT_EN_WIDTH … #define FRF_BB_TX_IPFIL18_PORT_EN_LBN … #define FRF_BB_TX_IPFIL18_PORT_EN_WIDTH … #define FRF_BB_TX_IPFIL17_PORT_EN_LBN … #define FRF_BB_TX_IPFIL17_PORT_EN_WIDTH … #define FRF_BB_TX_IPFIL16_PORT_EN_LBN … #define FRF_BB_TX_IPFIL16_PORT_EN_WIDTH … #define FRF_BB_TX_IPFIL15_PORT_EN_LBN … #define FRF_BB_TX_IPFIL15_PORT_EN_WIDTH … #define FRF_BB_TX_IPFIL14_PORT_EN_LBN … #define FRF_BB_TX_IPFIL14_PORT_EN_WIDTH … #define FRF_BB_TX_IPFIL13_PORT_EN_LBN … #define FRF_BB_TX_IPFIL13_PORT_EN_WIDTH … #define FRF_BB_TX_IPFIL12_PORT_EN_LBN … #define FRF_BB_TX_IPFIL12_PORT_EN_WIDTH … #define FRF_BB_TX_IPFIL11_PORT_EN_LBN … #define FRF_BB_TX_IPFIL11_PORT_EN_WIDTH … #define FRF_BB_TX_IPFIL10_PORT_EN_LBN … #define FRF_BB_TX_IPFIL10_PORT_EN_WIDTH … #define FRF_BB_TX_IPFIL9_PORT_EN_LBN … #define FRF_BB_TX_IPFIL9_PORT_EN_WIDTH … #define FRF_BB_TX_IPFIL8_PORT_EN_LBN … #define FRF_BB_TX_IPFIL8_PORT_EN_WIDTH … #define FRF_BB_TX_IPFIL7_PORT_EN_LBN … #define FRF_BB_TX_IPFIL7_PORT_EN_WIDTH … #define FRF_BB_TX_IPFIL6_PORT_EN_LBN … #define FRF_BB_TX_IPFIL6_PORT_EN_WIDTH … #define FRF_BB_TX_IPFIL5_PORT_EN_LBN … #define FRF_BB_TX_IPFIL5_PORT_EN_WIDTH … #define FRF_BB_TX_IPFIL4_PORT_EN_LBN … #define FRF_BB_TX_IPFIL4_PORT_EN_WIDTH … #define FRF_BB_TX_IPFIL3_PORT_EN_LBN … #define FRF_BB_TX_IPFIL3_PORT_EN_WIDTH … #define FRF_BB_TX_IPFIL2_PORT_EN_LBN … #define FRF_BB_TX_IPFIL2_PORT_EN_WIDTH … #define FRF_BB_TX_IPFIL1_PORT_EN_LBN … #define FRF_BB_TX_IPFIL1_PORT_EN_WIDTH … #define FRF_BB_TX_IPFIL0_PORT_EN_LBN … #define FRF_BB_TX_IPFIL0_PORT_EN_WIDTH … /* TX_IPFIL_TBL: Transmit IP source address filter table */ #define FR_BB_TX_IPFIL_TBL … #define FR_BB_TX_IPFIL_TBL_STEP … #define FR_BB_TX_IPFIL_TBL_ROWS … #define FRF_BB_TX_IPFIL_MASK_1_LBN … #define FRF_BB_TX_IPFIL_MASK_1_WIDTH … #define FRF_BB_TX_IP_SRC_ADR_1_LBN … #define FRF_BB_TX_IP_SRC_ADR_1_WIDTH … #define FRF_BB_TX_IPFIL_MASK_0_LBN … #define FRF_BB_TX_IPFIL_MASK_0_WIDTH … #define FRF_BB_TX_IP_SRC_ADR_0_LBN … #define FRF_BB_TX_IP_SRC_ADR_0_WIDTH … /* MD_TXD_REG: PHY management transmit data register */ #define FR_AB_MD_TXD … #define FRF_AB_MD_TXD_LBN … #define FRF_AB_MD_TXD_WIDTH … /* MD_RXD_REG: PHY management receive data register */ #define FR_AB_MD_RXD … #define FRF_AB_MD_RXD_LBN … #define FRF_AB_MD_RXD_WIDTH … /* MD_CS_REG: PHY management configuration & status register */ #define FR_AB_MD_CS … #define FRF_AB_MD_RD_EN_CMD_LBN … #define FRF_AB_MD_RD_EN_CMD_WIDTH … #define FRF_AB_MD_WR_EN_CMD_LBN … #define FRF_AB_MD_WR_EN_CMD_WIDTH … #define FRF_AB_MD_ADDR_CMD_LBN … #define FRF_AB_MD_ADDR_CMD_WIDTH … #define FRF_AB_MD_PT_LBN … #define FRF_AB_MD_PT_WIDTH … #define FRF_AB_MD_PL_LBN … #define FRF_AB_MD_PL_WIDTH … #define FRF_AB_MD_INT_CLR_LBN … #define FRF_AB_MD_INT_CLR_WIDTH … #define FRF_AB_MD_GC_LBN … #define FRF_AB_MD_GC_WIDTH … #define FRF_AB_MD_PRSP_LBN … #define FRF_AB_MD_PRSP_WIDTH … #define FRF_AB_MD_RIC_LBN … #define FRF_AB_MD_RIC_WIDTH … #define FRF_AB_MD_RDC_LBN … #define FRF_AB_MD_RDC_WIDTH … #define FRF_AB_MD_WRC_LBN … #define FRF_AB_MD_WRC_WIDTH … /* MD_PHY_ADR_REG: PHY management PHY address register */ #define FR_AB_MD_PHY_ADR … #define FRF_AB_MD_PHY_ADR_LBN … #define FRF_AB_MD_PHY_ADR_WIDTH … /* MD_ID_REG: PHY management ID register */ #define FR_AB_MD_ID … #define FRF_AB_MD_PRT_ADR_LBN … #define FRF_AB_MD_PRT_ADR_WIDTH … #define FRF_AB_MD_DEV_ADR_LBN … #define FRF_AB_MD_DEV_ADR_WIDTH … /* MD_STAT_REG: PHY management status & mask register */ #define FR_AB_MD_STAT … #define FRF_AB_MD_PINT_LBN … #define FRF_AB_MD_PINT_WIDTH … #define FRF_AB_MD_DONE_LBN … #define FRF_AB_MD_DONE_WIDTH … #define FRF_AB_MD_BSERR_LBN … #define FRF_AB_MD_BSERR_WIDTH … #define FRF_AB_MD_LNFL_LBN … #define FRF_AB_MD_LNFL_WIDTH … #define FRF_AB_MD_BSY_LBN … #define FRF_AB_MD_BSY_WIDTH … /* MAC_STAT_DMA_REG: Port MAC statistical counter DMA register */ #define FR_AB_MAC_STAT_DMA … #define FRF_AB_MAC_STAT_DMA_CMD_LBN … #define FRF_AB_MAC_STAT_DMA_CMD_WIDTH … #define FRF_AB_MAC_STAT_DMA_ADR_LBN … #define FRF_AB_MAC_STAT_DMA_ADR_WIDTH … /* MAC_CTRL_REG: Port MAC control register */ #define FR_AB_MAC_CTRL … #define FRF_AB_MAC_XOFF_VAL_LBN … #define FRF_AB_MAC_XOFF_VAL_WIDTH … #define FRF_BB_TXFIFO_DRAIN_EN_LBN … #define FRF_BB_TXFIFO_DRAIN_EN_WIDTH … #define FRF_AB_MAC_XG_DISTXCRC_LBN … #define FRF_AB_MAC_XG_DISTXCRC_WIDTH … #define FRF_AB_MAC_BCAD_ACPT_LBN … #define FRF_AB_MAC_BCAD_ACPT_WIDTH … #define FRF_AB_MAC_UC_PROM_LBN … #define FRF_AB_MAC_UC_PROM_WIDTH … #define FRF_AB_MAC_LINK_STATUS_LBN … #define FRF_AB_MAC_LINK_STATUS_WIDTH … #define FRF_AB_MAC_SPEED_LBN … #define FRF_AB_MAC_SPEED_WIDTH … #define FFE_AB_MAC_SPEED_10G … #define FFE_AB_MAC_SPEED_1G … #define FFE_AB_MAC_SPEED_100M … #define FFE_AB_MAC_SPEED_10M … /* GEN_MODE_REG: General Purpose mode register (external interrupt mask) */ #define FR_BB_GEN_MODE … #define FRF_BB_XFP_PHY_INT_POL_SEL_LBN … #define FRF_BB_XFP_PHY_INT_POL_SEL_WIDTH … #define FRF_BB_XG_PHY_INT_POL_SEL_LBN … #define FRF_BB_XG_PHY_INT_POL_SEL_WIDTH … #define FRF_BB_XFP_PHY_INT_MASK_LBN … #define FRF_BB_XFP_PHY_INT_MASK_WIDTH … #define FRF_BB_XG_PHY_INT_MASK_LBN … #define FRF_BB_XG_PHY_INT_MASK_WIDTH … /* MAC_MC_HASH_REG0: Multicast address hash table */ #define FR_AB_MAC_MC_HASH_REG0 … #define FRF_AB_MAC_MCAST_HASH0_LBN … #define FRF_AB_MAC_MCAST_HASH0_WIDTH … /* MAC_MC_HASH_REG1: Multicast address hash table */ #define FR_AB_MAC_MC_HASH_REG1 … #define FRF_AB_MAC_MCAST_HASH1_LBN … #define FRF_AB_MAC_MCAST_HASH1_WIDTH … /* GM_CFG1_REG: GMAC configuration register 1 */ #define FR_AB_GM_CFG1 … #define FRF_AB_GM_SW_RST_LBN … #define FRF_AB_GM_SW_RST_WIDTH … #define FRF_AB_GM_SIM_RST_LBN … #define FRF_AB_GM_SIM_RST_WIDTH … #define FRF_AB_GM_RST_RX_MAC_CTL_LBN … #define FRF_AB_GM_RST_RX_MAC_CTL_WIDTH … #define FRF_AB_GM_RST_TX_MAC_CTL_LBN … #define FRF_AB_GM_RST_TX_MAC_CTL_WIDTH … #define FRF_AB_GM_RST_RX_FUNC_LBN … #define FRF_AB_GM_RST_RX_FUNC_WIDTH … #define FRF_AB_GM_RST_TX_FUNC_LBN … #define FRF_AB_GM_RST_TX_FUNC_WIDTH … #define FRF_AB_GM_LOOP_LBN … #define FRF_AB_GM_LOOP_WIDTH … #define FRF_AB_GM_RX_FC_EN_LBN … #define FRF_AB_GM_RX_FC_EN_WIDTH … #define FRF_AB_GM_TX_FC_EN_LBN … #define FRF_AB_GM_TX_FC_EN_WIDTH … #define FRF_AB_GM_SYNC_RXEN_LBN … #define FRF_AB_GM_SYNC_RXEN_WIDTH … #define FRF_AB_GM_RX_EN_LBN … #define FRF_AB_GM_RX_EN_WIDTH … #define FRF_AB_GM_SYNC_TXEN_LBN … #define FRF_AB_GM_SYNC_TXEN_WIDTH … #define FRF_AB_GM_TX_EN_LBN … #define FRF_AB_GM_TX_EN_WIDTH … /* GM_CFG2_REG: GMAC configuration register 2 */ #define FR_AB_GM_CFG2 … #define FRF_AB_GM_PAMBL_LEN_LBN … #define FRF_AB_GM_PAMBL_LEN_WIDTH … #define FRF_AB_GM_IF_MODE_LBN … #define FRF_AB_GM_IF_MODE_WIDTH … #define FFE_AB_IF_MODE_BYTE_MODE … #define FFE_AB_IF_MODE_NIBBLE_MODE … #define FRF_AB_GM_HUGE_FRM_EN_LBN … #define FRF_AB_GM_HUGE_FRM_EN_WIDTH … #define FRF_AB_GM_LEN_CHK_LBN … #define FRF_AB_GM_LEN_CHK_WIDTH … #define FRF_AB_GM_PAD_CRC_EN_LBN … #define FRF_AB_GM_PAD_CRC_EN_WIDTH … #define FRF_AB_GM_CRC_EN_LBN … #define FRF_AB_GM_CRC_EN_WIDTH … #define FRF_AB_GM_FD_LBN … #define FRF_AB_GM_FD_WIDTH … /* GM_IPG_REG: GMAC IPG register */ #define FR_AB_GM_IPG … #define FRF_AB_GM_NONB2B_IPG1_LBN … #define FRF_AB_GM_NONB2B_IPG1_WIDTH … #define FRF_AB_GM_NONB2B_IPG2_LBN … #define FRF_AB_GM_NONB2B_IPG2_WIDTH … #define FRF_AB_GM_MIN_IPG_ENF_LBN … #define FRF_AB_GM_MIN_IPG_ENF_WIDTH … #define FRF_AB_GM_B2B_IPG_LBN … #define FRF_AB_GM_B2B_IPG_WIDTH … /* GM_HD_REG: GMAC half duplex register */ #define FR_AB_GM_HD … #define FRF_AB_GM_ALT_BOFF_VAL_LBN … #define FRF_AB_GM_ALT_BOFF_VAL_WIDTH … #define FRF_AB_GM_ALT_BOFF_EN_LBN … #define FRF_AB_GM_ALT_BOFF_EN_WIDTH … #define FRF_AB_GM_BP_NO_BOFF_LBN … #define FRF_AB_GM_BP_NO_BOFF_WIDTH … #define FRF_AB_GM_DIS_BOFF_LBN … #define FRF_AB_GM_DIS_BOFF_WIDTH … #define FRF_AB_GM_EXDEF_TX_EN_LBN … #define FRF_AB_GM_EXDEF_TX_EN_WIDTH … #define FRF_AB_GM_RTRY_LIMIT_LBN … #define FRF_AB_GM_RTRY_LIMIT_WIDTH … #define FRF_AB_GM_COL_WIN_LBN … #define FRF_AB_GM_COL_WIN_WIDTH … /* GM_MAX_FLEN_REG: GMAC maximum frame length register */ #define FR_AB_GM_MAX_FLEN … #define FRF_AB_GM_MAX_FLEN_LBN … #define FRF_AB_GM_MAX_FLEN_WIDTH … /* GM_TEST_REG: GMAC test register */ #define FR_AB_GM_TEST … #define FRF_AB_GM_MAX_BOFF_LBN … #define FRF_AB_GM_MAX_BOFF_WIDTH … #define FRF_AB_GM_REG_TX_FLOW_EN_LBN … #define FRF_AB_GM_REG_TX_FLOW_EN_WIDTH … #define FRF_AB_GM_TEST_PAUSE_LBN … #define FRF_AB_GM_TEST_PAUSE_WIDTH … #define FRF_AB_GM_SHORT_SLOT_LBN … #define FRF_AB_GM_SHORT_SLOT_WIDTH … /* GM_ADR1_REG: GMAC station address register 1 */ #define FR_AB_GM_ADR1 … #define FRF_AB_GM_ADR_B0_LBN … #define FRF_AB_GM_ADR_B0_WIDTH … #define FRF_AB_GM_ADR_B1_LBN … #define FRF_AB_GM_ADR_B1_WIDTH … #define FRF_AB_GM_ADR_B2_LBN … #define FRF_AB_GM_ADR_B2_WIDTH … #define FRF_AB_GM_ADR_B3_LBN … #define FRF_AB_GM_ADR_B3_WIDTH … /* GM_ADR2_REG: GMAC station address register 2 */ #define FR_AB_GM_ADR2 … #define FRF_AB_GM_ADR_B4_LBN … #define FRF_AB_GM_ADR_B4_WIDTH … #define FRF_AB_GM_ADR_B5_LBN … #define FRF_AB_GM_ADR_B5_WIDTH … /* GMF_CFG0_REG: GMAC FIFO configuration register 0 */ #define FR_AB_GMF_CFG0 … #define FRF_AB_GMF_FTFENRPLY_LBN … #define FRF_AB_GMF_FTFENRPLY_WIDTH … #define FRF_AB_GMF_STFENRPLY_LBN … #define FRF_AB_GMF_STFENRPLY_WIDTH … #define FRF_AB_GMF_FRFENRPLY_LBN … #define FRF_AB_GMF_FRFENRPLY_WIDTH … #define FRF_AB_GMF_SRFENRPLY_LBN … #define FRF_AB_GMF_SRFENRPLY_WIDTH … #define FRF_AB_GMF_WTMENRPLY_LBN … #define FRF_AB_GMF_WTMENRPLY_WIDTH … #define FRF_AB_GMF_FTFENREQ_LBN … #define FRF_AB_GMF_FTFENREQ_WIDTH … #define FRF_AB_GMF_STFENREQ_LBN … #define FRF_AB_GMF_STFENREQ_WIDTH … #define FRF_AB_GMF_FRFENREQ_LBN … #define FRF_AB_GMF_FRFENREQ_WIDTH … #define FRF_AB_GMF_SRFENREQ_LBN … #define FRF_AB_GMF_SRFENREQ_WIDTH … #define FRF_AB_GMF_WTMENREQ_LBN … #define FRF_AB_GMF_WTMENREQ_WIDTH … #define FRF_AB_GMF_HSTRSTFT_LBN … #define FRF_AB_GMF_HSTRSTFT_WIDTH … #define FRF_AB_GMF_HSTRSTST_LBN … #define FRF_AB_GMF_HSTRSTST_WIDTH … #define FRF_AB_GMF_HSTRSTFR_LBN … #define FRF_AB_GMF_HSTRSTFR_WIDTH … #define FRF_AB_GMF_HSTRSTSR_LBN … #define FRF_AB_GMF_HSTRSTSR_WIDTH … #define FRF_AB_GMF_HSTRSTWT_LBN … #define FRF_AB_GMF_HSTRSTWT_WIDTH … /* GMF_CFG1_REG: GMAC FIFO configuration register 1 */ #define FR_AB_GMF_CFG1 … #define FRF_AB_GMF_CFGFRTH_LBN … #define FRF_AB_GMF_CFGFRTH_WIDTH … #define FRF_AB_GMF_CFGXOFFRTX_LBN … #define FRF_AB_GMF_CFGXOFFRTX_WIDTH … /* GMF_CFG2_REG: GMAC FIFO configuration register 2 */ #define FR_AB_GMF_CFG2 … #define FRF_AB_GMF_CFGHWM_LBN … #define FRF_AB_GMF_CFGHWM_WIDTH … #define FRF_AB_GMF_CFGLWM_LBN … #define FRF_AB_GMF_CFGLWM_WIDTH … /* GMF_CFG3_REG: GMAC FIFO configuration register 3 */ #define FR_AB_GMF_CFG3 … #define FRF_AB_GMF_CFGHWMFT_LBN … #define FRF_AB_GMF_CFGHWMFT_WIDTH … #define FRF_AB_GMF_CFGFTTH_LBN … #define FRF_AB_GMF_CFGFTTH_WIDTH … /* GMF_CFG4_REG: GMAC FIFO configuration register 4 */ #define FR_AB_GMF_CFG4 … #define FRF_AB_GMF_HSTFLTRFRM_LBN … #define FRF_AB_GMF_HSTFLTRFRM_WIDTH … /* GMF_CFG5_REG: GMAC FIFO configuration register 5 */ #define FR_AB_GMF_CFG5 … #define FRF_AB_GMF_CFGHDPLX_LBN … #define FRF_AB_GMF_CFGHDPLX_WIDTH … #define FRF_AB_GMF_SRFULL_LBN … #define FRF_AB_GMF_SRFULL_WIDTH … #define FRF_AB_GMF_HSTSRFULLCLR_LBN … #define FRF_AB_GMF_HSTSRFULLCLR_WIDTH … #define FRF_AB_GMF_CFGBYTMODE_LBN … #define FRF_AB_GMF_CFGBYTMODE_WIDTH … #define FRF_AB_GMF_HSTDRPLT64_LBN … #define FRF_AB_GMF_HSTDRPLT64_WIDTH … #define FRF_AB_GMF_HSTFLTRFRMDC_LBN … #define FRF_AB_GMF_HSTFLTRFRMDC_WIDTH … /* TX_SRC_MAC_TBL: Transmit IP source address filter table */ #define FR_BB_TX_SRC_MAC_TBL … #define FR_BB_TX_SRC_MAC_TBL_STEP … #define FR_BB_TX_SRC_MAC_TBL_ROWS … #define FRF_BB_TX_SRC_MAC_ADR_1_LBN … #define FRF_BB_TX_SRC_MAC_ADR_1_WIDTH … #define FRF_BB_TX_SRC_MAC_ADR_0_LBN … #define FRF_BB_TX_SRC_MAC_ADR_0_WIDTH … /* TX_SRC_MAC_CTL_REG: Transmit MAC source address filter control */ #define FR_BB_TX_SRC_MAC_CTL … #define FRF_BB_TX_SRC_DROP_CTR_LBN … #define FRF_BB_TX_SRC_DROP_CTR_WIDTH … #define FRF_BB_TX_SRC_FLTR_EN_LBN … #define FRF_BB_TX_SRC_FLTR_EN_WIDTH … #define FRF_BB_TX_DROP_CTR_CLR_LBN … #define FRF_BB_TX_DROP_CTR_CLR_WIDTH … #define FRF_BB_TX_MAC_QID_SEL_LBN … #define FRF_BB_TX_MAC_QID_SEL_WIDTH … /* XM_ADR_LO_REG: XGMAC address register low */ #define FR_AB_XM_ADR_LO … #define FRF_AB_XM_ADR_LO_LBN … #define FRF_AB_XM_ADR_LO_WIDTH … /* XM_ADR_HI_REG: XGMAC address register high */ #define FR_AB_XM_ADR_HI … #define FRF_AB_XM_ADR_HI_LBN … #define FRF_AB_XM_ADR_HI_WIDTH … /* XM_GLB_CFG_REG: XGMAC global configuration */ #define FR_AB_XM_GLB_CFG … #define FRF_AB_XM_RMTFLT_GEN_LBN … #define FRF_AB_XM_RMTFLT_GEN_WIDTH … #define FRF_AB_XM_DEBUG_MODE_LBN … #define FRF_AB_XM_DEBUG_MODE_WIDTH … #define FRF_AB_XM_RX_STAT_EN_LBN … #define FRF_AB_XM_RX_STAT_EN_WIDTH … #define FRF_AB_XM_TX_STAT_EN_LBN … #define FRF_AB_XM_TX_STAT_EN_WIDTH … #define FRF_AB_XM_RX_JUMBO_MODE_LBN … #define FRF_AB_XM_RX_JUMBO_MODE_WIDTH … #define FRF_AB_XM_WAN_MODE_LBN … #define FRF_AB_XM_WAN_MODE_WIDTH … #define FRF_AB_XM_INTCLR_MODE_LBN … #define FRF_AB_XM_INTCLR_MODE_WIDTH … #define FRF_AB_XM_CORE_RST_LBN … #define FRF_AB_XM_CORE_RST_WIDTH … /* XM_TX_CFG_REG: XGMAC transmit configuration */ #define FR_AB_XM_TX_CFG … #define FRF_AB_XM_TX_PROG_LBN … #define FRF_AB_XM_TX_PROG_WIDTH … #define FRF_AB_XM_IPG_LBN … #define FRF_AB_XM_IPG_WIDTH … #define FRF_AB_XM_FCNTL_LBN … #define FRF_AB_XM_FCNTL_WIDTH … #define FRF_AB_XM_TXCRC_LBN … #define FRF_AB_XM_TXCRC_WIDTH … #define FRF_AB_XM_EDRC_LBN … #define FRF_AB_XM_EDRC_WIDTH … #define FRF_AB_XM_AUTO_PAD_LBN … #define FRF_AB_XM_AUTO_PAD_WIDTH … #define FRF_AB_XM_TX_PRMBL_LBN … #define FRF_AB_XM_TX_PRMBL_WIDTH … #define FRF_AB_XM_TXEN_LBN … #define FRF_AB_XM_TXEN_WIDTH … #define FRF_AB_XM_TX_RST_LBN … #define FRF_AB_XM_TX_RST_WIDTH … /* XM_RX_CFG_REG: XGMAC receive configuration */ #define FR_AB_XM_RX_CFG … #define FRF_AB_XM_PASS_LENERR_LBN … #define FRF_AB_XM_PASS_LENERR_WIDTH … #define FRF_AB_XM_PASS_CRC_ERR_LBN … #define FRF_AB_XM_PASS_CRC_ERR_WIDTH … #define FRF_AB_XM_PASS_PRMBLE_ERR_LBN … #define FRF_AB_XM_PASS_PRMBLE_ERR_WIDTH … #define FRF_AB_XM_REJ_BCAST_LBN … #define FRF_AB_XM_REJ_BCAST_WIDTH … #define FRF_AB_XM_ACPT_ALL_MCAST_LBN … #define FRF_AB_XM_ACPT_ALL_MCAST_WIDTH … #define FRF_AB_XM_ACPT_ALL_UCAST_LBN … #define FRF_AB_XM_ACPT_ALL_UCAST_WIDTH … #define FRF_AB_XM_AUTO_DEPAD_LBN … #define FRF_AB_XM_AUTO_DEPAD_WIDTH … #define FRF_AB_XM_RXCRC_LBN … #define FRF_AB_XM_RXCRC_WIDTH … #define FRF_AB_XM_RX_PRMBL_LBN … #define FRF_AB_XM_RX_PRMBL_WIDTH … #define FRF_AB_XM_RXEN_LBN … #define FRF_AB_XM_RXEN_WIDTH … #define FRF_AB_XM_RX_RST_LBN … #define FRF_AB_XM_RX_RST_WIDTH … /* XM_MGT_INT_MASK: documentation to be written for sum_XM_MGT_INT_MASK */ #define FR_AB_XM_MGT_INT_MASK … #define FRF_AB_XM_MSK_STA_INTR_LBN … #define FRF_AB_XM_MSK_STA_INTR_WIDTH … #define FRF_AB_XM_MSK_STAT_CNTR_HF_LBN … #define FRF_AB_XM_MSK_STAT_CNTR_HF_WIDTH … #define FRF_AB_XM_MSK_STAT_CNTR_OF_LBN … #define FRF_AB_XM_MSK_STAT_CNTR_OF_WIDTH … #define FRF_AB_XM_MSK_PRMBLE_ERR_LBN … #define FRF_AB_XM_MSK_PRMBLE_ERR_WIDTH … #define FRF_AB_XM_MSK_RMTFLT_LBN … #define FRF_AB_XM_MSK_RMTFLT_WIDTH … #define FRF_AB_XM_MSK_LCLFLT_LBN … #define FRF_AB_XM_MSK_LCLFLT_WIDTH … /* XM_FC_REG: XGMAC flow control register */ #define FR_AB_XM_FC … #define FRF_AB_XM_PAUSE_TIME_LBN … #define FRF_AB_XM_PAUSE_TIME_WIDTH … #define FRF_AB_XM_RX_MAC_STAT_LBN … #define FRF_AB_XM_RX_MAC_STAT_WIDTH … #define FRF_AB_XM_TX_MAC_STAT_LBN … #define FRF_AB_XM_TX_MAC_STAT_WIDTH … #define FRF_AB_XM_MCNTL_PASS_LBN … #define FRF_AB_XM_MCNTL_PASS_WIDTH … #define FRF_AB_XM_REJ_CNTL_UCAST_LBN … #define FRF_AB_XM_REJ_CNTL_UCAST_WIDTH … #define FRF_AB_XM_REJ_CNTL_MCAST_LBN … #define FRF_AB_XM_REJ_CNTL_MCAST_WIDTH … #define FRF_AB_XM_ZPAUSE_LBN … #define FRF_AB_XM_ZPAUSE_WIDTH … #define FRF_AB_XM_XMIT_PAUSE_LBN … #define FRF_AB_XM_XMIT_PAUSE_WIDTH … #define FRF_AB_XM_DIS_FCNTL_LBN … #define FRF_AB_XM_DIS_FCNTL_WIDTH … /* XM_PAUSE_TIME_REG: XGMAC pause time register */ #define FR_AB_XM_PAUSE_TIME … #define FRF_AB_XM_TX_PAUSE_CNT_LBN … #define FRF_AB_XM_TX_PAUSE_CNT_WIDTH … #define FRF_AB_XM_RX_PAUSE_CNT_LBN … #define FRF_AB_XM_RX_PAUSE_CNT_WIDTH … /* XM_TX_PARAM_REG: XGMAC transmit parameter register */ #define FR_AB_XM_TX_PARAM … #define FRF_AB_XM_TX_JUMBO_MODE_LBN … #define FRF_AB_XM_TX_JUMBO_MODE_WIDTH … #define FRF_AB_XM_MAX_TX_FRM_SIZE_HI_LBN … #define FRF_AB_XM_MAX_TX_FRM_SIZE_HI_WIDTH … #define FRF_AB_XM_MAX_TX_FRM_SIZE_LO_LBN … #define FRF_AB_XM_MAX_TX_FRM_SIZE_LO_WIDTH … #define FRF_AB_XM_PAD_CHAR_LBN … #define FRF_AB_XM_PAD_CHAR_WIDTH … /* XM_RX_PARAM_REG: XGMAC receive parameter register */ #define FR_AB_XM_RX_PARAM … #define FRF_AB_XM_MAX_RX_FRM_SIZE_HI_LBN … #define FRF_AB_XM_MAX_RX_FRM_SIZE_HI_WIDTH … #define FRF_AB_XM_MAX_RX_FRM_SIZE_LO_LBN … #define FRF_AB_XM_MAX_RX_FRM_SIZE_LO_WIDTH … /* XM_MGT_INT_MSK_REG: XGMAC management interrupt mask register */ #define FR_AB_XM_MGT_INT_MSK … #define FRF_AB_XM_STAT_CNTR_OF_LBN … #define FRF_AB_XM_STAT_CNTR_OF_WIDTH … #define FRF_AB_XM_STAT_CNTR_HF_LBN … #define FRF_AB_XM_STAT_CNTR_HF_WIDTH … #define FRF_AB_XM_PRMBLE_ERR_LBN … #define FRF_AB_XM_PRMBLE_ERR_WIDTH … #define FRF_AB_XM_RMTFLT_LBN … #define FRF_AB_XM_RMTFLT_WIDTH … #define FRF_AB_XM_LCLFLT_LBN … #define FRF_AB_XM_LCLFLT_WIDTH … /* XX_PWR_RST_REG: XGXS/XAUI powerdown/reset register */ #define FR_AB_XX_PWR_RST … #define FRF_AB_XX_PWRDND_SIG_LBN … #define FRF_AB_XX_PWRDND_SIG_WIDTH … #define FRF_AB_XX_PWRDNC_SIG_LBN … #define FRF_AB_XX_PWRDNC_SIG_WIDTH … #define FRF_AB_XX_PWRDNB_SIG_LBN … #define FRF_AB_XX_PWRDNB_SIG_WIDTH … #define FRF_AB_XX_PWRDNA_SIG_LBN … #define FRF_AB_XX_PWRDNA_SIG_WIDTH … #define FRF_AB_XX_SIM_MODE_LBN … #define FRF_AB_XX_SIM_MODE_WIDTH … #define FRF_AB_XX_RSTPLLCD_SIG_LBN … #define FRF_AB_XX_RSTPLLCD_SIG_WIDTH … #define FRF_AB_XX_RSTPLLAB_SIG_LBN … #define FRF_AB_XX_RSTPLLAB_SIG_WIDTH … #define FRF_AB_XX_RESETD_SIG_LBN … #define FRF_AB_XX_RESETD_SIG_WIDTH … #define FRF_AB_XX_RESETC_SIG_LBN … #define FRF_AB_XX_RESETC_SIG_WIDTH … #define FRF_AB_XX_RESETB_SIG_LBN … #define FRF_AB_XX_RESETB_SIG_WIDTH … #define FRF_AB_XX_RESETA_SIG_LBN … #define FRF_AB_XX_RESETA_SIG_WIDTH … #define FRF_AB_XX_RSTXGXSRX_SIG_LBN … #define FRF_AB_XX_RSTXGXSRX_SIG_WIDTH … #define FRF_AB_XX_RSTXGXSTX_SIG_LBN … #define FRF_AB_XX_RSTXGXSTX_SIG_WIDTH … #define FRF_AB_XX_SD_RST_ACT_LBN … #define FRF_AB_XX_SD_RST_ACT_WIDTH … #define FRF_AB_XX_PWRDND_EN_LBN … #define FRF_AB_XX_PWRDND_EN_WIDTH … #define FRF_AB_XX_PWRDNC_EN_LBN … #define FRF_AB_XX_PWRDNC_EN_WIDTH … #define FRF_AB_XX_PWRDNB_EN_LBN … #define FRF_AB_XX_PWRDNB_EN_WIDTH … #define FRF_AB_XX_PWRDNA_EN_LBN … #define FRF_AB_XX_PWRDNA_EN_WIDTH … #define FRF_AB_XX_RSTPLLCD_EN_LBN … #define FRF_AB_XX_RSTPLLCD_EN_WIDTH … #define FRF_AB_XX_RSTPLLAB_EN_LBN … #define FRF_AB_XX_RSTPLLAB_EN_WIDTH … #define FRF_AB_XX_RESETD_EN_LBN … #define FRF_AB_XX_RESETD_EN_WIDTH … #define FRF_AB_XX_RESETC_EN_LBN … #define FRF_AB_XX_RESETC_EN_WIDTH … #define FRF_AB_XX_RESETB_EN_LBN … #define FRF_AB_XX_RESETB_EN_WIDTH … #define FRF_AB_XX_RESETA_EN_LBN … #define FRF_AB_XX_RESETA_EN_WIDTH … #define FRF_AB_XX_RSTXGXSRX_EN_LBN … #define FRF_AB_XX_RSTXGXSRX_EN_WIDTH … #define FRF_AB_XX_RSTXGXSTX_EN_LBN … #define FRF_AB_XX_RSTXGXSTX_EN_WIDTH … #define FRF_AB_XX_RST_XX_EN_LBN … #define FRF_AB_XX_RST_XX_EN_WIDTH … /* XX_SD_CTL_REG: XGXS/XAUI powerdown/reset control register */ #define FR_AB_XX_SD_CTL … #define FRF_AB_XX_TERMADJ1_LBN … #define FRF_AB_XX_TERMADJ1_WIDTH … #define FRF_AB_XX_TERMADJ0_LBN … #define FRF_AB_XX_TERMADJ0_WIDTH … #define FRF_AB_XX_HIDRVD_LBN … #define FRF_AB_XX_HIDRVD_WIDTH … #define FRF_AB_XX_LODRVD_LBN … #define FRF_AB_XX_LODRVD_WIDTH … #define FRF_AB_XX_HIDRVC_LBN … #define FRF_AB_XX_HIDRVC_WIDTH … #define FRF_AB_XX_LODRVC_LBN … #define FRF_AB_XX_LODRVC_WIDTH … #define FRF_AB_XX_HIDRVB_LBN … #define FRF_AB_XX_HIDRVB_WIDTH … #define FRF_AB_XX_LODRVB_LBN … #define FRF_AB_XX_LODRVB_WIDTH … #define FRF_AB_XX_HIDRVA_LBN … #define FRF_AB_XX_HIDRVA_WIDTH … #define FRF_AB_XX_LODRVA_LBN … #define FRF_AB_XX_LODRVA_WIDTH … #define FRF_AB_XX_LPBKD_LBN … #define FRF_AB_XX_LPBKD_WIDTH … #define FRF_AB_XX_LPBKC_LBN … #define FRF_AB_XX_LPBKC_WIDTH … #define FRF_AB_XX_LPBKB_LBN … #define FRF_AB_XX_LPBKB_WIDTH … #define FRF_AB_XX_LPBKA_LBN … #define FRF_AB_XX_LPBKA_WIDTH … /* XX_TXDRV_CTL_REG: XAUI SerDes transmit drive control register */ #define FR_AB_XX_TXDRV_CTL … #define FRF_AB_XX_DEQD_LBN … #define FRF_AB_XX_DEQD_WIDTH … #define FRF_AB_XX_DEQC_LBN … #define FRF_AB_XX_DEQC_WIDTH … #define FRF_AB_XX_DEQB_LBN … #define FRF_AB_XX_DEQB_WIDTH … #define FRF_AB_XX_DEQA_LBN … #define FRF_AB_XX_DEQA_WIDTH … #define FRF_AB_XX_DTXD_LBN … #define FRF_AB_XX_DTXD_WIDTH … #define FRF_AB_XX_DTXC_LBN … #define FRF_AB_XX_DTXC_WIDTH … #define FRF_AB_XX_DTXB_LBN … #define FRF_AB_XX_DTXB_WIDTH … #define FRF_AB_XX_DTXA_LBN … #define FRF_AB_XX_DTXA_WIDTH … /* XX_PRBS_CTL_REG: documentation to be written for sum_XX_PRBS_CTL_REG */ #define FR_AB_XX_PRBS_CTL … #define FRF_AB_XX_CH3_RX_PRBS_SEL_LBN … #define FRF_AB_XX_CH3_RX_PRBS_SEL_WIDTH … #define FRF_AB_XX_CH3_RX_PRBS_INV_LBN … #define FRF_AB_XX_CH3_RX_PRBS_INV_WIDTH … #define FRF_AB_XX_CH3_RX_PRBS_CHKEN_LBN … #define FRF_AB_XX_CH3_RX_PRBS_CHKEN_WIDTH … #define FRF_AB_XX_CH2_RX_PRBS_SEL_LBN … #define FRF_AB_XX_CH2_RX_PRBS_SEL_WIDTH … #define FRF_AB_XX_CH2_RX_PRBS_INV_LBN … #define FRF_AB_XX_CH2_RX_PRBS_INV_WIDTH … #define FRF_AB_XX_CH2_RX_PRBS_CHKEN_LBN … #define FRF_AB_XX_CH2_RX_PRBS_CHKEN_WIDTH … #define FRF_AB_XX_CH1_RX_PRBS_SEL_LBN … #define FRF_AB_XX_CH1_RX_PRBS_SEL_WIDTH … #define FRF_AB_XX_CH1_RX_PRBS_INV_LBN … #define FRF_AB_XX_CH1_RX_PRBS_INV_WIDTH … #define FRF_AB_XX_CH1_RX_PRBS_CHKEN_LBN … #define FRF_AB_XX_CH1_RX_PRBS_CHKEN_WIDTH … #define FRF_AB_XX_CH0_RX_PRBS_SEL_LBN … #define FRF_AB_XX_CH0_RX_PRBS_SEL_WIDTH … #define FRF_AB_XX_CH0_RX_PRBS_INV_LBN … #define FRF_AB_XX_CH0_RX_PRBS_INV_WIDTH … #define FRF_AB_XX_CH0_RX_PRBS_CHKEN_LBN … #define FRF_AB_XX_CH0_RX_PRBS_CHKEN_WIDTH … #define FRF_AB_XX_CH3_TX_PRBS_SEL_LBN … #define FRF_AB_XX_CH3_TX_PRBS_SEL_WIDTH … #define FRF_AB_XX_CH3_TX_PRBS_INV_LBN … #define FRF_AB_XX_CH3_TX_PRBS_INV_WIDTH … #define FRF_AB_XX_CH3_TX_PRBS_CHKEN_LBN … #define FRF_AB_XX_CH3_TX_PRBS_CHKEN_WIDTH … #define FRF_AB_XX_CH2_TX_PRBS_SEL_LBN … #define FRF_AB_XX_CH2_TX_PRBS_SEL_WIDTH … #define FRF_AB_XX_CH2_TX_PRBS_INV_LBN … #define FRF_AB_XX_CH2_TX_PRBS_INV_WIDTH … #define FRF_AB_XX_CH2_TX_PRBS_CHKEN_LBN … #define FRF_AB_XX_CH2_TX_PRBS_CHKEN_WIDTH … #define FRF_AB_XX_CH1_TX_PRBS_SEL_LBN … #define FRF_AB_XX_CH1_TX_PRBS_SEL_WIDTH … #define FRF_AB_XX_CH1_TX_PRBS_INV_LBN … #define FRF_AB_XX_CH1_TX_PRBS_INV_WIDTH … #define FRF_AB_XX_CH1_TX_PRBS_CHKEN_LBN … #define FRF_AB_XX_CH1_TX_PRBS_CHKEN_WIDTH … #define FRF_AB_XX_CH0_TX_PRBS_SEL_LBN … #define FRF_AB_XX_CH0_TX_PRBS_SEL_WIDTH … #define FRF_AB_XX_CH0_TX_PRBS_INV_LBN … #define FRF_AB_XX_CH0_TX_PRBS_INV_WIDTH … #define FRF_AB_XX_CH0_TX_PRBS_CHKEN_LBN … #define FRF_AB_XX_CH0_TX_PRBS_CHKEN_WIDTH … /* XX_PRBS_CHK_REG: documentation to be written for sum_XX_PRBS_CHK_REG */ #define FR_AB_XX_PRBS_CHK … #define FRF_AB_XX_REV_LB_EN_LBN … #define FRF_AB_XX_REV_LB_EN_WIDTH … #define FRF_AB_XX_CH3_DEG_DET_LBN … #define FRF_AB_XX_CH3_DEG_DET_WIDTH … #define FRF_AB_XX_CH3_LFSR_LOCK_IND_LBN … #define FRF_AB_XX_CH3_LFSR_LOCK_IND_WIDTH … #define FRF_AB_XX_CH3_PRBS_FRUN_LBN … #define FRF_AB_XX_CH3_PRBS_FRUN_WIDTH … #define FRF_AB_XX_CH3_ERR_CHK_LBN … #define FRF_AB_XX_CH3_ERR_CHK_WIDTH … #define FRF_AB_XX_CH2_DEG_DET_LBN … #define FRF_AB_XX_CH2_DEG_DET_WIDTH … #define FRF_AB_XX_CH2_LFSR_LOCK_IND_LBN … #define FRF_AB_XX_CH2_LFSR_LOCK_IND_WIDTH … #define FRF_AB_XX_CH2_PRBS_FRUN_LBN … #define FRF_AB_XX_CH2_PRBS_FRUN_WIDTH … #define FRF_AB_XX_CH2_ERR_CHK_LBN … #define FRF_AB_XX_CH2_ERR_CHK_WIDTH … #define FRF_AB_XX_CH1_DEG_DET_LBN … #define FRF_AB_XX_CH1_DEG_DET_WIDTH … #define FRF_AB_XX_CH1_LFSR_LOCK_IND_LBN … #define FRF_AB_XX_CH1_LFSR_LOCK_IND_WIDTH … #define FRF_AB_XX_CH1_PRBS_FRUN_LBN … #define FRF_AB_XX_CH1_PRBS_FRUN_WIDTH … #define FRF_AB_XX_CH1_ERR_CHK_LBN … #define FRF_AB_XX_CH1_ERR_CHK_WIDTH … #define FRF_AB_XX_CH0_DEG_DET_LBN … #define FRF_AB_XX_CH0_DEG_DET_WIDTH … #define FRF_AB_XX_CH0_LFSR_LOCK_IND_LBN … #define FRF_AB_XX_CH0_LFSR_LOCK_IND_WIDTH … #define FRF_AB_XX_CH0_PRBS_FRUN_LBN … #define FRF_AB_XX_CH0_PRBS_FRUN_WIDTH … #define FRF_AB_XX_CH0_ERR_CHK_LBN … #define FRF_AB_XX_CH0_ERR_CHK_WIDTH … /* XX_PRBS_ERR_REG: documentation to be written for sum_XX_PRBS_ERR_REG */ #define FR_AB_XX_PRBS_ERR … #define FRF_AB_XX_CH3_PRBS_ERR_CNT_LBN … #define FRF_AB_XX_CH3_PRBS_ERR_CNT_WIDTH … #define FRF_AB_XX_CH2_PRBS_ERR_CNT_LBN … #define FRF_AB_XX_CH2_PRBS_ERR_CNT_WIDTH … #define FRF_AB_XX_CH1_PRBS_ERR_CNT_LBN … #define FRF_AB_XX_CH1_PRBS_ERR_CNT_WIDTH … #define FRF_AB_XX_CH0_PRBS_ERR_CNT_LBN … #define FRF_AB_XX_CH0_PRBS_ERR_CNT_WIDTH … /* XX_CORE_STAT_REG: XAUI XGXS core status register */ #define FR_AB_XX_CORE_STAT … #define FRF_AB_XX_FORCE_SIG3_LBN … #define FRF_AB_XX_FORCE_SIG3_WIDTH … #define FRF_AB_XX_FORCE_SIG3_VAL_LBN … #define FRF_AB_XX_FORCE_SIG3_VAL_WIDTH … #define FRF_AB_XX_FORCE_SIG2_LBN … #define FRF_AB_XX_FORCE_SIG2_WIDTH … #define FRF_AB_XX_FORCE_SIG2_VAL_LBN … #define FRF_AB_XX_FORCE_SIG2_VAL_WIDTH … #define FRF_AB_XX_FORCE_SIG1_LBN … #define FRF_AB_XX_FORCE_SIG1_WIDTH … #define FRF_AB_XX_FORCE_SIG1_VAL_LBN … #define FRF_AB_XX_FORCE_SIG1_VAL_WIDTH … #define FRF_AB_XX_FORCE_SIG0_LBN … #define FRF_AB_XX_FORCE_SIG0_WIDTH … #define FRF_AB_XX_FORCE_SIG0_VAL_LBN … #define FRF_AB_XX_FORCE_SIG0_VAL_WIDTH … #define FRF_AB_XX_XGXS_LB_EN_LBN … #define FRF_AB_XX_XGXS_LB_EN_WIDTH … #define FRF_AB_XX_XGMII_LB_EN_LBN … #define FRF_AB_XX_XGMII_LB_EN_WIDTH … #define FRF_AB_XX_MATCH_FAULT_LBN … #define FRF_AB_XX_MATCH_FAULT_WIDTH … #define FRF_AB_XX_ALIGN_DONE_LBN … #define FRF_AB_XX_ALIGN_DONE_WIDTH … #define FRF_AB_XX_SYNC_STAT3_LBN … #define FRF_AB_XX_SYNC_STAT3_WIDTH … #define FRF_AB_XX_SYNC_STAT2_LBN … #define FRF_AB_XX_SYNC_STAT2_WIDTH … #define FRF_AB_XX_SYNC_STAT1_LBN … #define FRF_AB_XX_SYNC_STAT1_WIDTH … #define FRF_AB_XX_SYNC_STAT0_LBN … #define FRF_AB_XX_SYNC_STAT0_WIDTH … #define FRF_AB_XX_COMMA_DET_CH3_LBN … #define FRF_AB_XX_COMMA_DET_CH3_WIDTH … #define FRF_AB_XX_COMMA_DET_CH2_LBN … #define FRF_AB_XX_COMMA_DET_CH2_WIDTH … #define FRF_AB_XX_COMMA_DET_CH1_LBN … #define FRF_AB_XX_COMMA_DET_CH1_WIDTH … #define FRF_AB_XX_COMMA_DET_CH0_LBN … #define FRF_AB_XX_COMMA_DET_CH0_WIDTH … #define FRF_AB_XX_CGRP_ALIGN_CH3_LBN … #define FRF_AB_XX_CGRP_ALIGN_CH3_WIDTH … #define FRF_AB_XX_CGRP_ALIGN_CH2_LBN … #define FRF_AB_XX_CGRP_ALIGN_CH2_WIDTH … #define FRF_AB_XX_CGRP_ALIGN_CH1_LBN … #define FRF_AB_XX_CGRP_ALIGN_CH1_WIDTH … #define FRF_AB_XX_CGRP_ALIGN_CH0_LBN … #define FRF_AB_XX_CGRP_ALIGN_CH0_WIDTH … #define FRF_AB_XX_CHAR_ERR_CH3_LBN … #define FRF_AB_XX_CHAR_ERR_CH3_WIDTH … #define FRF_AB_XX_CHAR_ERR_CH2_LBN … #define FRF_AB_XX_CHAR_ERR_CH2_WIDTH … #define FRF_AB_XX_CHAR_ERR_CH1_LBN … #define FRF_AB_XX_CHAR_ERR_CH1_WIDTH … #define FRF_AB_XX_CHAR_ERR_CH0_LBN … #define FRF_AB_XX_CHAR_ERR_CH0_WIDTH … #define FRF_AB_XX_DISPERR_CH3_LBN … #define FRF_AB_XX_DISPERR_CH3_WIDTH … #define FRF_AB_XX_DISPERR_CH2_LBN … #define FRF_AB_XX_DISPERR_CH2_WIDTH … #define FRF_AB_XX_DISPERR_CH1_LBN … #define FRF_AB_XX_DISPERR_CH1_WIDTH … #define FRF_AB_XX_DISPERR_CH0_LBN … #define FRF_AB_XX_DISPERR_CH0_WIDTH … /* RX_DESC_PTR_TBL_KER: Receive descriptor pointer table */ #define FR_AA_RX_DESC_PTR_TBL_KER … #define FR_AA_RX_DESC_PTR_TBL_KER_STEP … #define FR_AA_RX_DESC_PTR_TBL_KER_ROWS … /* RX_DESC_PTR_TBL: Receive descriptor pointer table */ #define FR_BZ_RX_DESC_PTR_TBL … #define FR_BZ_RX_DESC_PTR_TBL_STEP … #define FR_BB_RX_DESC_PTR_TBL_ROWS … #define FR_CZ_RX_DESC_PTR_TBL_ROWS … #define FRF_CZ_RX_HDR_SPLIT_LBN … #define FRF_CZ_RX_HDR_SPLIT_WIDTH … #define FRF_AA_RX_RESET_LBN … #define FRF_AA_RX_RESET_WIDTH … #define FRF_AZ_RX_ISCSI_DDIG_EN_LBN … #define FRF_AZ_RX_ISCSI_DDIG_EN_WIDTH … #define FRF_AZ_RX_ISCSI_HDIG_EN_LBN … #define FRF_AZ_RX_ISCSI_HDIG_EN_WIDTH … #define FRF_AZ_RX_DESC_PREF_ACT_LBN … #define FRF_AZ_RX_DESC_PREF_ACT_WIDTH … #define FRF_AZ_RX_DC_HW_RPTR_LBN … #define FRF_AZ_RX_DC_HW_RPTR_WIDTH … #define FRF_AZ_RX_DESCQ_HW_RPTR_LBN … #define FRF_AZ_RX_DESCQ_HW_RPTR_WIDTH … #define FRF_AZ_RX_DESCQ_SW_WPTR_LBN … #define FRF_AZ_RX_DESCQ_SW_WPTR_WIDTH … #define FRF_AZ_RX_DESCQ_BUF_BASE_ID_LBN … #define FRF_AZ_RX_DESCQ_BUF_BASE_ID_WIDTH … #define FRF_AZ_RX_DESCQ_EVQ_ID_LBN … #define FRF_AZ_RX_DESCQ_EVQ_ID_WIDTH … #define FRF_AZ_RX_DESCQ_OWNER_ID_LBN … #define FRF_AZ_RX_DESCQ_OWNER_ID_WIDTH … #define FRF_AZ_RX_DESCQ_LABEL_LBN … #define FRF_AZ_RX_DESCQ_LABEL_WIDTH … #define FRF_AZ_RX_DESCQ_SIZE_LBN … #define FRF_AZ_RX_DESCQ_SIZE_WIDTH … #define FFE_AZ_RX_DESCQ_SIZE_4K … #define FFE_AZ_RX_DESCQ_SIZE_2K … #define FFE_AZ_RX_DESCQ_SIZE_1K … #define FFE_AZ_RX_DESCQ_SIZE_512 … #define FRF_AZ_RX_DESCQ_TYPE_LBN … #define FRF_AZ_RX_DESCQ_TYPE_WIDTH … #define FRF_AZ_RX_DESCQ_JUMBO_LBN … #define FRF_AZ_RX_DESCQ_JUMBO_WIDTH … #define FRF_AZ_RX_DESCQ_EN_LBN … #define FRF_AZ_RX_DESCQ_EN_WIDTH … /* TX_DESC_PTR_TBL_KER: Transmit descriptor pointer */ #define FR_AA_TX_DESC_PTR_TBL_KER … #define FR_AA_TX_DESC_PTR_TBL_KER_STEP … #define FR_AA_TX_DESC_PTR_TBL_KER_ROWS … /* TX_DESC_PTR_TBL: Transmit descriptor pointer */ #define FR_BZ_TX_DESC_PTR_TBL … #define FR_BZ_TX_DESC_PTR_TBL_STEP … #define FR_BB_TX_DESC_PTR_TBL_ROWS … #define FR_CZ_TX_DESC_PTR_TBL_ROWS … #define FRF_CZ_TX_DPT_Q_MASK_WIDTH_LBN … #define FRF_CZ_TX_DPT_Q_MASK_WIDTH_WIDTH … #define FRF_CZ_TX_DPT_ETH_FILT_EN_LBN … #define FRF_CZ_TX_DPT_ETH_FILT_EN_WIDTH … #define FRF_CZ_TX_DPT_IP_FILT_EN_LBN … #define FRF_CZ_TX_DPT_IP_FILT_EN_WIDTH … #define FRF_BZ_TX_NON_IP_DROP_DIS_LBN … #define FRF_BZ_TX_NON_IP_DROP_DIS_WIDTH … #define FRF_BZ_TX_IP_CHKSM_DIS_LBN … #define FRF_BZ_TX_IP_CHKSM_DIS_WIDTH … #define FRF_BZ_TX_TCP_CHKSM_DIS_LBN … #define FRF_BZ_TX_TCP_CHKSM_DIS_WIDTH … #define FRF_AZ_TX_DESCQ_EN_LBN … #define FRF_AZ_TX_DESCQ_EN_WIDTH … #define FRF_AZ_TX_ISCSI_DDIG_EN_LBN … #define FRF_AZ_TX_ISCSI_DDIG_EN_WIDTH … #define FRF_AZ_TX_ISCSI_HDIG_EN_LBN … #define FRF_AZ_TX_ISCSI_HDIG_EN_WIDTH … #define FRF_AZ_TX_DC_HW_RPTR_LBN … #define FRF_AZ_TX_DC_HW_RPTR_WIDTH … #define FRF_AZ_TX_DESCQ_HW_RPTR_LBN … #define FRF_AZ_TX_DESCQ_HW_RPTR_WIDTH … #define FRF_AZ_TX_DESCQ_SW_WPTR_LBN … #define FRF_AZ_TX_DESCQ_SW_WPTR_WIDTH … #define FRF_AZ_TX_DESCQ_BUF_BASE_ID_LBN … #define FRF_AZ_TX_DESCQ_BUF_BASE_ID_WIDTH … #define FRF_AZ_TX_DESCQ_EVQ_ID_LBN … #define FRF_AZ_TX_DESCQ_EVQ_ID_WIDTH … #define FRF_AZ_TX_DESCQ_OWNER_ID_LBN … #define FRF_AZ_TX_DESCQ_OWNER_ID_WIDTH … #define FRF_AZ_TX_DESCQ_LABEL_LBN … #define FRF_AZ_TX_DESCQ_LABEL_WIDTH … #define FRF_AZ_TX_DESCQ_SIZE_LBN … #define FRF_AZ_TX_DESCQ_SIZE_WIDTH … #define FFE_AZ_TX_DESCQ_SIZE_4K … #define FFE_AZ_TX_DESCQ_SIZE_2K … #define FFE_AZ_TX_DESCQ_SIZE_1K … #define FFE_AZ_TX_DESCQ_SIZE_512 … #define FRF_AZ_TX_DESCQ_TYPE_LBN … #define FRF_AZ_TX_DESCQ_TYPE_WIDTH … #define FRF_AZ_TX_DESCQ_FLUSH_LBN … #define FRF_AZ_TX_DESCQ_FLUSH_WIDTH … /* EVQ_PTR_TBL_KER: Event queue pointer table */ #define FR_AA_EVQ_PTR_TBL_KER … #define FR_AA_EVQ_PTR_TBL_KER_STEP … #define FR_AA_EVQ_PTR_TBL_KER_ROWS … /* EVQ_PTR_TBL: Event queue pointer table */ #define FR_BZ_EVQ_PTR_TBL … #define FR_BZ_EVQ_PTR_TBL_STEP … #define FR_CZ_EVQ_PTR_TBL_ROWS … #define FR_BB_EVQ_PTR_TBL_ROWS … #define FRF_BZ_EVQ_RPTR_IGN_LBN … #define FRF_BZ_EVQ_RPTR_IGN_WIDTH … #define FRF_AB_EVQ_WKUP_OR_INT_EN_LBN … #define FRF_AB_EVQ_WKUP_OR_INT_EN_WIDTH … #define FRF_CZ_EVQ_DOS_PROTECT_EN_LBN … #define FRF_CZ_EVQ_DOS_PROTECT_EN_WIDTH … #define FRF_AZ_EVQ_NXT_WPTR_LBN … #define FRF_AZ_EVQ_NXT_WPTR_WIDTH … #define FRF_AZ_EVQ_EN_LBN … #define FRF_AZ_EVQ_EN_WIDTH … #define FRF_AZ_EVQ_SIZE_LBN … #define FRF_AZ_EVQ_SIZE_WIDTH … #define FFE_AZ_EVQ_SIZE_32K … #define FFE_AZ_EVQ_SIZE_16K … #define FFE_AZ_EVQ_SIZE_8K … #define FFE_AZ_EVQ_SIZE_4K … #define FFE_AZ_EVQ_SIZE_2K … #define FFE_AZ_EVQ_SIZE_1K … #define FFE_AZ_EVQ_SIZE_512 … #define FRF_AZ_EVQ_BUF_BASE_ID_LBN … #define FRF_AZ_EVQ_BUF_BASE_ID_WIDTH … /* BUF_HALF_TBL_KER: Buffer table in half buffer table mode direct access by driver */ #define FR_AA_BUF_HALF_TBL_KER … #define FR_AA_BUF_HALF_TBL_KER_STEP … #define FR_AA_BUF_HALF_TBL_KER_ROWS … /* BUF_HALF_TBL: Buffer table in half buffer table mode direct access by driver */ #define FR_BZ_BUF_HALF_TBL … #define FR_BZ_BUF_HALF_TBL_STEP … #define FR_CZ_BUF_HALF_TBL_ROWS … #define FR_BB_BUF_HALF_TBL_ROWS … #define FRF_AZ_BUF_ADR_HBUF_ODD_LBN … #define FRF_AZ_BUF_ADR_HBUF_ODD_WIDTH … #define FRF_AZ_BUF_OWNER_ID_HBUF_ODD_LBN … #define FRF_AZ_BUF_OWNER_ID_HBUF_ODD_WIDTH … #define FRF_AZ_BUF_ADR_HBUF_EVEN_LBN … #define FRF_AZ_BUF_ADR_HBUF_EVEN_WIDTH … #define FRF_AZ_BUF_OWNER_ID_HBUF_EVEN_LBN … #define FRF_AZ_BUF_OWNER_ID_HBUF_EVEN_WIDTH … /* BUF_FULL_TBL_KER: Buffer table in full buffer table mode direct access by driver */ #define FR_AA_BUF_FULL_TBL_KER … #define FR_AA_BUF_FULL_TBL_KER_STEP … #define FR_AA_BUF_FULL_TBL_KER_ROWS … /* BUF_FULL_TBL: Buffer table in full buffer table mode direct access by driver */ #define FR_BZ_BUF_FULL_TBL … #define FR_BZ_BUF_FULL_TBL_STEP … #define FR_CZ_BUF_FULL_TBL_ROWS … #define FR_BB_BUF_FULL_TBL_ROWS … #define FRF_AZ_BUF_FULL_UNUSED_LBN … #define FRF_AZ_BUF_FULL_UNUSED_WIDTH … #define FRF_AZ_IP_DAT_BUF_SIZE_LBN … #define FRF_AZ_IP_DAT_BUF_SIZE_WIDTH … #define FRF_AZ_BUF_ADR_REGION_LBN … #define FRF_AZ_BUF_ADR_REGION_WIDTH … #define FFE_AZ_BUF_ADR_REGN3 … #define FFE_AZ_BUF_ADR_REGN2 … #define FFE_AZ_BUF_ADR_REGN1 … #define FFE_AZ_BUF_ADR_REGN0 … #define FRF_AZ_BUF_ADR_FBUF_LBN … #define FRF_AZ_BUF_ADR_FBUF_WIDTH … #define FRF_AZ_BUF_OWNER_ID_FBUF_LBN … #define FRF_AZ_BUF_OWNER_ID_FBUF_WIDTH … /* RX_FILTER_TBL0: TCP/IPv4 Receive filter table */ #define FR_BZ_RX_FILTER_TBL0 … #define FR_BZ_RX_FILTER_TBL0_STEP … #define FR_BZ_RX_FILTER_TBL0_ROWS … /* RX_FILTER_TBL1: TCP/IPv4 Receive filter table */ #define FR_BB_RX_FILTER_TBL1 … #define FR_BB_RX_FILTER_TBL1_STEP … #define FR_BB_RX_FILTER_TBL1_ROWS … #define FRF_BZ_RSS_EN_LBN … #define FRF_BZ_RSS_EN_WIDTH … #define FRF_BZ_SCATTER_EN_LBN … #define FRF_BZ_SCATTER_EN_WIDTH … #define FRF_BZ_TCP_UDP_LBN … #define FRF_BZ_TCP_UDP_WIDTH … #define FRF_BZ_RXQ_ID_LBN … #define FRF_BZ_RXQ_ID_WIDTH … #define FRF_BZ_DEST_IP_LBN … #define FRF_BZ_DEST_IP_WIDTH … #define FRF_BZ_DEST_PORT_TCP_LBN … #define FRF_BZ_DEST_PORT_TCP_WIDTH … #define FRF_BZ_SRC_IP_LBN … #define FRF_BZ_SRC_IP_WIDTH … #define FRF_BZ_SRC_TCP_DEST_UDP_LBN … #define FRF_BZ_SRC_TCP_DEST_UDP_WIDTH … /* RX_MAC_FILTER_TBL0: Receive Ethernet filter table */ #define FR_CZ_RX_MAC_FILTER_TBL0 … #define FR_CZ_RX_MAC_FILTER_TBL0_STEP … #define FR_CZ_RX_MAC_FILTER_TBL0_ROWS … #define FRF_CZ_RMFT_RSS_EN_LBN … #define FRF_CZ_RMFT_RSS_EN_WIDTH … #define FRF_CZ_RMFT_SCATTER_EN_LBN … #define FRF_CZ_RMFT_SCATTER_EN_WIDTH … #define FRF_CZ_RMFT_IP_OVERRIDE_LBN … #define FRF_CZ_RMFT_IP_OVERRIDE_WIDTH … #define FRF_CZ_RMFT_RXQ_ID_LBN … #define FRF_CZ_RMFT_RXQ_ID_WIDTH … #define FRF_CZ_RMFT_WILDCARD_MATCH_LBN … #define FRF_CZ_RMFT_WILDCARD_MATCH_WIDTH … #define FRF_CZ_RMFT_DEST_MAC_LBN … #define FRF_CZ_RMFT_DEST_MAC_WIDTH … #define FRF_CZ_RMFT_VLAN_ID_LBN … #define FRF_CZ_RMFT_VLAN_ID_WIDTH … /* TIMER_TBL: Timer table */ #define FR_BZ_TIMER_TBL … #define FR_BZ_TIMER_TBL_STEP … #define FR_CZ_TIMER_TBL_ROWS … #define FR_BB_TIMER_TBL_ROWS … #define FRF_CZ_TIMER_Q_EN_LBN … #define FRF_CZ_TIMER_Q_EN_WIDTH … #define FRF_CZ_INT_ARMD_LBN … #define FRF_CZ_INT_ARMD_WIDTH … #define FRF_CZ_INT_PEND_LBN … #define FRF_CZ_INT_PEND_WIDTH … #define FRF_CZ_HOST_NOTIFY_MODE_LBN … #define FRF_CZ_HOST_NOTIFY_MODE_WIDTH … #define FRF_CZ_RELOAD_TIMER_VAL_LBN … #define FRF_CZ_RELOAD_TIMER_VAL_WIDTH … #define FRF_CZ_TIMER_MODE_LBN … #define FRF_CZ_TIMER_MODE_WIDTH … #define FFE_CZ_TIMER_MODE_INT_HLDOFF … #define FFE_CZ_TIMER_MODE_TRIG_START … #define FFE_CZ_TIMER_MODE_IMMED_START … #define FFE_CZ_TIMER_MODE_DIS … #define FRF_BB_TIMER_MODE_LBN … #define FRF_BB_TIMER_MODE_WIDTH … #define FFE_BB_TIMER_MODE_INT_HLDOFF … #define FFE_BB_TIMER_MODE_TRIG_START … #define FFE_BB_TIMER_MODE_IMMED_START … #define FFE_BB_TIMER_MODE_DIS … #define FRF_CZ_TIMER_VAL_LBN … #define FRF_CZ_TIMER_VAL_WIDTH … #define FRF_BB_TIMER_VAL_LBN … #define FRF_BB_TIMER_VAL_WIDTH … /* TX_PACE_TBL: Transmit pacing table */ #define FR_BZ_TX_PACE_TBL … #define FR_BZ_TX_PACE_TBL_STEP … #define FR_CZ_TX_PACE_TBL_ROWS … #define FR_BB_TX_PACE_TBL_ROWS … #define FRF_BZ_TX_PACE_LBN … #define FRF_BZ_TX_PACE_WIDTH … /* RX_INDIRECTION_TBL: RX Indirection Table */ #define FR_BZ_RX_INDIRECTION_TBL … #define FR_BZ_RX_INDIRECTION_TBL_STEP … #define FR_BZ_RX_INDIRECTION_TBL_ROWS … #define FRF_BZ_IT_QUEUE_LBN … #define FRF_BZ_IT_QUEUE_WIDTH … /* TX_FILTER_TBL0: TCP/IPv4 Transmit filter table */ #define FR_CZ_TX_FILTER_TBL0 … #define FR_CZ_TX_FILTER_TBL0_STEP … #define FR_CZ_TX_FILTER_TBL0_ROWS … #define FRF_CZ_TIFT_TCP_UDP_LBN … #define FRF_CZ_TIFT_TCP_UDP_WIDTH … #define FRF_CZ_TIFT_TXQ_ID_LBN … #define FRF_CZ_TIFT_TXQ_ID_WIDTH … #define FRF_CZ_TIFT_DEST_IP_LBN … #define FRF_CZ_TIFT_DEST_IP_WIDTH … #define FRF_CZ_TIFT_DEST_PORT_TCP_LBN … #define FRF_CZ_TIFT_DEST_PORT_TCP_WIDTH … #define FRF_CZ_TIFT_SRC_IP_LBN … #define FRF_CZ_TIFT_SRC_IP_WIDTH … #define FRF_CZ_TIFT_SRC_TCP_DEST_UDP_LBN … #define FRF_CZ_TIFT_SRC_TCP_DEST_UDP_WIDTH … /* TX_MAC_FILTER_TBL0: Transmit Ethernet filter table */ #define FR_CZ_TX_MAC_FILTER_TBL0 … #define FR_CZ_TX_MAC_FILTER_TBL0_STEP … #define FR_CZ_TX_MAC_FILTER_TBL0_ROWS … #define FRF_CZ_TMFT_TXQ_ID_LBN … #define FRF_CZ_TMFT_TXQ_ID_WIDTH … #define FRF_CZ_TMFT_WILDCARD_MATCH_LBN … #define FRF_CZ_TMFT_WILDCARD_MATCH_WIDTH … #define FRF_CZ_TMFT_SRC_MAC_LBN … #define FRF_CZ_TMFT_SRC_MAC_WIDTH … #define FRF_CZ_TMFT_VLAN_ID_LBN … #define FRF_CZ_TMFT_VLAN_ID_WIDTH … /* MC_TREG_SMEM: MC Shared Memory */ #define FR_CZ_MC_TREG_SMEM … #define FR_CZ_MC_TREG_SMEM_STEP … #define FR_CZ_MC_TREG_SMEM_ROWS … #define FRF_CZ_MC_TREG_SMEM_ROW_LBN … #define FRF_CZ_MC_TREG_SMEM_ROW_WIDTH … /* MSIX_VECTOR_TABLE: MSIX Vector Table */ #define FR_BB_MSIX_VECTOR_TABLE … #define FR_BZ_MSIX_VECTOR_TABLE_STEP … #define FR_BB_MSIX_VECTOR_TABLE_ROWS … /* MSIX_VECTOR_TABLE: MSIX Vector Table */ #define FR_CZ_MSIX_VECTOR_TABLE … /* FR_BZ_MSIX_VECTOR_TABLE_STEP 16 */ #define FR_CZ_MSIX_VECTOR_TABLE_ROWS … #define FRF_BZ_MSIX_VECTOR_RESERVED_LBN … #define FRF_BZ_MSIX_VECTOR_RESERVED_WIDTH … #define FRF_BZ_MSIX_VECTOR_MASK_LBN … #define FRF_BZ_MSIX_VECTOR_MASK_WIDTH … #define FRF_BZ_MSIX_MESSAGE_DATA_LBN … #define FRF_BZ_MSIX_MESSAGE_DATA_WIDTH … #define FRF_BZ_MSIX_MESSAGE_ADDRESS_HI_LBN … #define FRF_BZ_MSIX_MESSAGE_ADDRESS_HI_WIDTH … #define FRF_BZ_MSIX_MESSAGE_ADDRESS_LO_LBN … #define FRF_BZ_MSIX_MESSAGE_ADDRESS_LO_WIDTH … /* MSIX_PBA_TABLE: MSIX Pending Bit Array */ #define FR_BB_MSIX_PBA_TABLE … #define FR_BZ_MSIX_PBA_TABLE_STEP … #define FR_BB_MSIX_PBA_TABLE_ROWS … /* MSIX_PBA_TABLE: MSIX Pending Bit Array */ #define FR_CZ_MSIX_PBA_TABLE … /* FR_BZ_MSIX_PBA_TABLE_STEP 4 */ #define FR_CZ_MSIX_PBA_TABLE_ROWS … #define FRF_BZ_MSIX_PBA_PEND_DWORD_LBN … #define FRF_BZ_MSIX_PBA_PEND_DWORD_WIDTH … /* SRM_DBG_REG: SRAM debug access */ #define FR_BZ_SRM_DBG … #define FR_BZ_SRM_DBG_STEP … #define FR_CZ_SRM_DBG_ROWS … #define FR_BB_SRM_DBG_ROWS … #define FRF_BZ_SRM_DBG_LBN … #define FRF_BZ_SRM_DBG_WIDTH … /* TB_MSIX_PBA_TABLE: MSIX Pending Bit Array */ #define FR_CZ_TB_MSIX_PBA_TABLE … #define FR_CZ_TB_MSIX_PBA_TABLE_STEP … #define FR_CZ_TB_MSIX_PBA_TABLE_ROWS … #define FRF_CZ_TB_MSIX_PBA_PEND_DWORD_LBN … #define FRF_CZ_TB_MSIX_PBA_PEND_DWORD_WIDTH … /* DRIVER_EV */ #define FSF_AZ_DRIVER_EV_SUBCODE_LBN … #define FSF_AZ_DRIVER_EV_SUBCODE_WIDTH … #define FSE_BZ_TX_DSC_ERROR_EV … #define FSE_BZ_RX_DSC_ERROR_EV … #define FSE_AA_RX_RECOVER_EV … #define FSE_AZ_TIMER_EV … #define FSE_AZ_TX_PKT_NON_TCP_UDP … #define FSE_AZ_WAKE_UP_EV … #define FSE_AZ_SRM_UPD_DONE_EV … #define FSE_AB_EVQ_NOT_EN_EV … #define FSE_AZ_EVQ_INIT_DONE_EV … #define FSE_AZ_RX_DESCQ_FLS_DONE_EV … #define FSE_AZ_TX_DESCQ_FLS_DONE_EV … #define FSF_AZ_DRIVER_EV_SUBDATA_LBN … #define FSF_AZ_DRIVER_EV_SUBDATA_WIDTH … /* EVENT_ENTRY */ #define FSF_AZ_EV_CODE_LBN … #define FSF_AZ_EV_CODE_WIDTH … #define FSE_CZ_EV_CODE_MCDI_EV … #define FSE_CZ_EV_CODE_USER_EV … #define FSE_AZ_EV_CODE_DRV_GEN_EV … #define FSE_AZ_EV_CODE_GLOBAL_EV … #define FSE_AZ_EV_CODE_DRIVER_EV … #define FSE_AZ_EV_CODE_TX_EV … #define FSE_AZ_EV_CODE_RX_EV … #define FSF_AZ_EV_DATA_LBN … #define FSF_AZ_EV_DATA_WIDTH … /* GLOBAL_EV */ #define FSF_BB_GLB_EV_RX_RECOVERY_LBN … #define FSF_BB_GLB_EV_RX_RECOVERY_WIDTH … #define FSF_AA_GLB_EV_RX_RECOVERY_LBN … #define FSF_AA_GLB_EV_RX_RECOVERY_WIDTH … #define FSF_BB_GLB_EV_XG_MGT_INTR_LBN … #define FSF_BB_GLB_EV_XG_MGT_INTR_WIDTH … #define FSF_AB_GLB_EV_XFP_PHY0_INTR_LBN … #define FSF_AB_GLB_EV_XFP_PHY0_INTR_WIDTH … #define FSF_AB_GLB_EV_XG_PHY0_INTR_LBN … #define FSF_AB_GLB_EV_XG_PHY0_INTR_WIDTH … #define FSF_AB_GLB_EV_G_PHY0_INTR_LBN … #define FSF_AB_GLB_EV_G_PHY0_INTR_WIDTH … /* LEGACY_INT_VEC */ #define FSF_AZ_NET_IVEC_FATAL_INT_LBN … #define FSF_AZ_NET_IVEC_FATAL_INT_WIDTH … #define FSF_AZ_NET_IVEC_INT_Q_LBN … #define FSF_AZ_NET_IVEC_INT_Q_WIDTH … #define FSF_AZ_NET_IVEC_INT_FLAG_LBN … #define FSF_AZ_NET_IVEC_INT_FLAG_WIDTH … #define FSF_AZ_NET_IVEC_EVQ_FIFO_HF_LBN … #define FSF_AZ_NET_IVEC_EVQ_FIFO_HF_WIDTH … #define FSF_AZ_NET_IVEC_EVQ_FIFO_AF_LBN … #define FSF_AZ_NET_IVEC_EVQ_FIFO_AF_WIDTH … /* MC_XGMAC_FLTR_RULE_DEF */ #define FSF_CZ_MC_XFRC_MODE_LBN … #define FSF_CZ_MC_XFRC_MODE_WIDTH … #define FSE_CZ_MC_XFRC_MODE_LAYERED … #define FSE_CZ_MC_XFRC_MODE_SIMPLE … #define FSF_CZ_MC_XFRC_HASH_LBN … #define FSF_CZ_MC_XFRC_HASH_WIDTH … #define FSF_CZ_MC_XFRC_LAYER4_BYTE_MASK_LBN … #define FSF_CZ_MC_XFRC_LAYER4_BYTE_MASK_WIDTH … #define FSF_CZ_MC_XFRC_LAYER3_BYTE_MASK_LBN … #define FSF_CZ_MC_XFRC_LAYER3_BYTE_MASK_WIDTH … #define FSF_CZ_MC_XFRC_LAYER2_OR_SIMPLE_BYTE_MASK_LBN … #define FSF_CZ_MC_XFRC_LAYER2_OR_SIMPLE_BYTE_MASK_WIDTH … /* RX_EV */ #define FSF_CZ_RX_EV_PKT_NOT_PARSED_LBN … #define FSF_CZ_RX_EV_PKT_NOT_PARSED_WIDTH … #define FSF_CZ_RX_EV_IPV6_PKT_LBN … #define FSF_CZ_RX_EV_IPV6_PKT_WIDTH … #define FSF_AZ_RX_EV_PKT_OK_LBN … #define FSF_AZ_RX_EV_PKT_OK_WIDTH … #define FSF_AZ_RX_EV_PAUSE_FRM_ERR_LBN … #define FSF_AZ_RX_EV_PAUSE_FRM_ERR_WIDTH … #define FSF_AZ_RX_EV_BUF_OWNER_ID_ERR_LBN … #define FSF_AZ_RX_EV_BUF_OWNER_ID_ERR_WIDTH … #define FSF_AZ_RX_EV_IP_FRAG_ERR_LBN … #define FSF_AZ_RX_EV_IP_FRAG_ERR_WIDTH … #define FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR_LBN … #define FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR_WIDTH … #define FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR_LBN … #define FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR_WIDTH … #define FSF_AZ_RX_EV_ETH_CRC_ERR_LBN … #define FSF_AZ_RX_EV_ETH_CRC_ERR_WIDTH … #define FSF_AZ_RX_EV_FRM_TRUNC_LBN … #define FSF_AZ_RX_EV_FRM_TRUNC_WIDTH … #define FSF_AA_RX_EV_DRIB_NIB_LBN … #define FSF_AA_RX_EV_DRIB_NIB_WIDTH … #define FSF_AZ_RX_EV_TOBE_DISC_LBN … #define FSF_AZ_RX_EV_TOBE_DISC_WIDTH … #define FSF_AZ_RX_EV_PKT_TYPE_LBN … #define FSF_AZ_RX_EV_PKT_TYPE_WIDTH … #define FSE_AZ_RX_EV_PKT_TYPE_VLAN_JUMBO … #define FSE_AZ_RX_EV_PKT_TYPE_VLAN_LLC … #define FSE_AZ_RX_EV_PKT_TYPE_VLAN … #define FSE_AZ_RX_EV_PKT_TYPE_JUMBO … #define FSE_AZ_RX_EV_PKT_TYPE_LLC … #define FSE_AZ_RX_EV_PKT_TYPE_ETH … #define FSF_AZ_RX_EV_HDR_TYPE_LBN … #define FSF_AZ_RX_EV_HDR_TYPE_WIDTH … #define FSE_AZ_RX_EV_HDR_TYPE_OTHER … #define FSE_AB_RX_EV_HDR_TYPE_IPV4_OTHER … #define FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_OTHER … #define FSE_AB_RX_EV_HDR_TYPE_IPV4_UDP … #define FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_UDP … #define FSE_AB_RX_EV_HDR_TYPE_IPV4_TCP … #define FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_TCP … #define FSF_AZ_RX_EV_DESC_Q_EMPTY_LBN … #define FSF_AZ_RX_EV_DESC_Q_EMPTY_WIDTH … #define FSF_AZ_RX_EV_MCAST_HASH_MATCH_LBN … #define FSF_AZ_RX_EV_MCAST_HASH_MATCH_WIDTH … #define FSF_AZ_RX_EV_MCAST_PKT_LBN … #define FSF_AZ_RX_EV_MCAST_PKT_WIDTH … #define FSF_AA_RX_EV_RECOVERY_FLAG_LBN … #define FSF_AA_RX_EV_RECOVERY_FLAG_WIDTH … #define FSF_AZ_RX_EV_Q_LABEL_LBN … #define FSF_AZ_RX_EV_Q_LABEL_WIDTH … #define FSF_AZ_RX_EV_JUMBO_CONT_LBN … #define FSF_AZ_RX_EV_JUMBO_CONT_WIDTH … #define FSF_AZ_RX_EV_PORT_LBN … #define FSF_AZ_RX_EV_PORT_WIDTH … #define FSF_AZ_RX_EV_BYTE_CNT_LBN … #define FSF_AZ_RX_EV_BYTE_CNT_WIDTH … #define FSF_AZ_RX_EV_SOP_LBN … #define FSF_AZ_RX_EV_SOP_WIDTH … #define FSF_AZ_RX_EV_ISCSI_PKT_OK_LBN … #define FSF_AZ_RX_EV_ISCSI_PKT_OK_WIDTH … #define FSF_AZ_RX_EV_ISCSI_DDIG_ERR_LBN … #define FSF_AZ_RX_EV_ISCSI_DDIG_ERR_WIDTH … #define FSF_AZ_RX_EV_ISCSI_HDIG_ERR_LBN … #define FSF_AZ_RX_EV_ISCSI_HDIG_ERR_WIDTH … #define FSF_AZ_RX_EV_DESC_PTR_LBN … #define FSF_AZ_RX_EV_DESC_PTR_WIDTH … /* RX_KER_DESC */ #define FSF_AZ_RX_KER_BUF_SIZE_LBN … #define FSF_AZ_RX_KER_BUF_SIZE_WIDTH … #define FSF_AZ_RX_KER_BUF_REGION_LBN … #define FSF_AZ_RX_KER_BUF_REGION_WIDTH … #define FSF_AZ_RX_KER_BUF_ADDR_LBN … #define FSF_AZ_RX_KER_BUF_ADDR_WIDTH … /* RX_USER_DESC */ #define FSF_AZ_RX_USER_2BYTE_OFFSET_LBN … #define FSF_AZ_RX_USER_2BYTE_OFFSET_WIDTH … #define FSF_AZ_RX_USER_BUF_ID_LBN … #define FSF_AZ_RX_USER_BUF_ID_WIDTH … /* TX_EV */ #define FSF_AZ_TX_EV_PKT_ERR_LBN … #define FSF_AZ_TX_EV_PKT_ERR_WIDTH … #define FSF_AZ_TX_EV_PKT_TOO_BIG_LBN … #define FSF_AZ_TX_EV_PKT_TOO_BIG_WIDTH … #define FSF_AZ_TX_EV_Q_LABEL_LBN … #define FSF_AZ_TX_EV_Q_LABEL_WIDTH … #define FSF_AZ_TX_EV_PORT_LBN … #define FSF_AZ_TX_EV_PORT_WIDTH … #define FSF_AZ_TX_EV_WQ_FF_FULL_LBN … #define FSF_AZ_TX_EV_WQ_FF_FULL_WIDTH … #define FSF_AZ_TX_EV_BUF_OWNER_ID_ERR_LBN … #define FSF_AZ_TX_EV_BUF_OWNER_ID_ERR_WIDTH … #define FSF_AZ_TX_EV_COMP_LBN … #define FSF_AZ_TX_EV_COMP_WIDTH … #define FSF_AZ_TX_EV_DESC_PTR_LBN … #define FSF_AZ_TX_EV_DESC_PTR_WIDTH … /* TX_KER_DESC */ #define FSF_AZ_TX_KER_CONT_LBN … #define FSF_AZ_TX_KER_CONT_WIDTH … #define FSF_AZ_TX_KER_BYTE_COUNT_LBN … #define FSF_AZ_TX_KER_BYTE_COUNT_WIDTH … #define FSF_AZ_TX_KER_BUF_REGION_LBN … #define FSF_AZ_TX_KER_BUF_REGION_WIDTH … #define FSF_AZ_TX_KER_BUF_ADDR_LBN … #define FSF_AZ_TX_KER_BUF_ADDR_WIDTH … /* TX_USER_DESC */ #define FSF_AZ_TX_USER_SW_EV_EN_LBN … #define FSF_AZ_TX_USER_SW_EV_EN_WIDTH … #define FSF_AZ_TX_USER_CONT_LBN … #define FSF_AZ_TX_USER_CONT_WIDTH … #define FSF_AZ_TX_USER_BYTE_CNT_LBN … #define FSF_AZ_TX_USER_BYTE_CNT_WIDTH … #define FSF_AZ_TX_USER_BUF_ID_LBN … #define FSF_AZ_TX_USER_BUF_ID_WIDTH … #define FSF_AZ_TX_USER_BYTE_OFS_LBN … #define FSF_AZ_TX_USER_BYTE_OFS_WIDTH … /* USER_EV */ #define FSF_CZ_USER_QID_LBN … #define FSF_CZ_USER_QID_WIDTH … #define FSF_CZ_USER_EV_REG_VALUE_LBN … #define FSF_CZ_USER_EV_REG_VALUE_WIDTH … /************************************************************************** * * Falcon B0 PCIe core indirect registers * ************************************************************************** */ #define FPCR_BB_PCIE_DEVICE_CTRL_STAT … #define FPCR_BB_PCIE_LINK_CTRL_STAT … #define FPCR_BB_ACK_RPL_TIMER … #define FPCRF_BB_ACK_TL_LBN … #define FPCRF_BB_ACK_TL_WIDTH … #define FPCRF_BB_RPL_TL_LBN … #define FPCRF_BB_RPL_TL_WIDTH … #define FPCR_BB_ACK_FREQ … #define FPCRF_BB_ACK_FREQ_LBN … #define FPCRF_BB_ACK_FREQ_WIDTH … /************************************************************************** * * Pseudo-registers and fields * ************************************************************************** */ /* Interrupt acknowledge work-around register (A0/A1 only) */ #define FR_AA_WORK_AROUND_BROKEN_PCI_READS … /* EE_SPI_HCMD_REG: SPI host command register */ /* Values for the EE_SPI_HCMD_SF_SEL register field */ #define FFE_AB_SPI_DEVICE_EEPROM … #define FFE_AB_SPI_DEVICE_FLASH … /* NIC_STAT_REG: NIC status register */ #define FRF_AB_STRAP_10G_LBN … #define FRF_AB_STRAP_10G_WIDTH … #define FRF_AA_STRAP_PCIE_LBN … #define FRF_AA_STRAP_PCIE_WIDTH … /* FATAL_INTR_REG_KER: Fatal interrupt register for Kernel */ #define FRF_AZ_FATAL_INTR_LBN … #define FRF_AZ_FATAL_INTR_WIDTH … /* SRM_CFG_REG: SRAM configuration register */ /* We treat the number of SRAM banks and bank size as a single field */ #define FRF_AZ_SRM_NB_SZ_LBN … #define FRF_AZ_SRM_NB_SZ_WIDTH … #define FFE_AB_SRM_NB1_SZ2M … #define FFE_AB_SRM_NB1_SZ4M … #define FFE_AB_SRM_NB1_SZ8M … #define FFE_AB_SRM_NB_SZ_DEF … #define FFE_AB_SRM_NB2_SZ4M … #define FFE_AB_SRM_NB2_SZ8M … #define FFE_AB_SRM_NB2_SZ16M … #define FFE_AB_SRM_NB_SZ_RES … /* RX_DESC_UPD_REGP0: Receive descriptor update register. */ /* We write just the last dword of these registers */ #define FR_AZ_RX_DESC_UPD_DWORD_P0 … #define FRF_AZ_RX_DESC_WPTR_DWORD_LBN … #define FRF_AZ_RX_DESC_WPTR_DWORD_WIDTH … /* TX_DESC_UPD_REGP0: Transmit descriptor update register. */ #define FR_AZ_TX_DESC_UPD_DWORD_P0 … #define FRF_AZ_TX_DESC_WPTR_DWORD_LBN … #define FRF_AZ_TX_DESC_WPTR_DWORD_WIDTH … /* GMF_CFG4_REG: GMAC FIFO configuration register 4 */ #define FRF_AB_GMF_HSTFLTRFRM_PAUSE_LBN … #define FRF_AB_GMF_HSTFLTRFRM_PAUSE_WIDTH … /* GMF_CFG5_REG: GMAC FIFO configuration register 5 */ #define FRF_AB_GMF_HSTFLTRFRMDC_PAUSE_LBN … #define FRF_AB_GMF_HSTFLTRFRMDC_PAUSE_WIDTH … /* XM_TX_PARAM_REG: XGMAC transmit parameter register */ #define FRF_AB_XM_MAX_TX_FRM_SIZE_LBN … #define FRF_AB_XM_MAX_TX_FRM_SIZE_WIDTH … /* XM_RX_PARAM_REG: XGMAC receive parameter register */ #define FRF_AB_XM_MAX_RX_FRM_SIZE_LBN … #define FRF_AB_XM_MAX_RX_FRM_SIZE_WIDTH … /* XX_TXDRV_CTL_REG: XAUI SerDes transmit drive control register */ /* Default values */ #define FFE_AB_XX_TXDRV_DEQ_DEF … #define FFE_AB_XX_TXDRV_DTX_DEF … #define FFE_AB_XX_SD_CTL_DRV_DEF … /* XX_CORE_STAT_REG: XAUI XGXS core status register */ /* XGXS all-lanes status fields */ #define FRF_AB_XX_SYNC_STAT_LBN … #define FRF_AB_XX_SYNC_STAT_WIDTH … #define FRF_AB_XX_COMMA_DET_LBN … #define FRF_AB_XX_COMMA_DET_WIDTH … #define FRF_AB_XX_CHAR_ERR_LBN … #define FRF_AB_XX_CHAR_ERR_WIDTH … #define FRF_AB_XX_DISPERR_LBN … #define FRF_AB_XX_DISPERR_WIDTH … #define FFE_AB_XX_STAT_ALL_LANES … #define FRF_AB_XX_FORCE_SIG_LBN … #define FRF_AB_XX_FORCE_SIG_WIDTH … #define FFE_AB_XX_FORCE_SIG_ALL_LANES … /* RX_MAC_FILTER_TBL0 */ /* RMFT_DEST_MAC is wider than 32 bits */ #define FRF_CZ_RMFT_DEST_MAC_LO_LBN … #define FRF_CZ_RMFT_DEST_MAC_LO_WIDTH … #define FRF_CZ_RMFT_DEST_MAC_HI_LBN … #define FRF_CZ_RMFT_DEST_MAC_HI_WIDTH … /* TX_MAC_FILTER_TBL0 */ /* TMFT_SRC_MAC is wider than 32 bits */ #define FRF_CZ_TMFT_SRC_MAC_LO_LBN … #define FRF_CZ_TMFT_SRC_MAC_LO_WIDTH … #define FRF_CZ_TMFT_SRC_MAC_HI_LBN … #define FRF_CZ_TMFT_SRC_MAC_HI_WIDTH … /* TX_PACE_TBL */ /* Values >20 are documented as reserved, but will result in a queue going * into the fast bin with a pace value of zero. */ #define FFE_BZ_TX_PACE_OFF … #define FFE_BZ_TX_PACE_RESERVED … /* DRIVER_EV */ /* Sub-fields of an RX flush completion event */ #define FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL_LBN … #define FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL_WIDTH … #define FSF_AZ_DRIVER_EV_RX_DESCQ_ID_LBN … #define FSF_AZ_DRIVER_EV_RX_DESCQ_ID_WIDTH … /* EVENT_ENTRY */ /* Magic number field for event test */ #define FSF_AZ_DRV_GEN_EV_MAGIC_LBN … #define FSF_AZ_DRV_GEN_EV_MAGIC_WIDTH … /* RX packet prefix */ #define FS_BZ_RX_PREFIX_HASH_OFST … #define FS_BZ_RX_PREFIX_SIZE … #endif /* EFX_FARCH_REGS_H */
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