/* SPDX-License-Identifier: GPL-2.0-only */ /**************************************************************************** * Driver for Solarflare network controllers and boards * Copyright 2005-2006 Fen Systems Ltd. * Copyright 2006-2013 Solarflare Communications Inc. */ #ifndef EFX_IO_H #define EFX_IO_H #include <linux/io.h> #include <linux/spinlock.h> /************************************************************************** * * NIC register I/O * ************************************************************************** * * Notes on locking strategy for the Falcon architecture: * * Many CSRs are very wide and cannot be read or written atomically. * Writes from the host are buffered by the Bus Interface Unit (BIU) * up to 128 bits. Whenever the host writes part of such a register, * the BIU collects the written value and does not write to the * underlying register until all 4 dwords have been written. A * similar buffering scheme applies to host access to the NIC's 64-bit * SRAM. * * Writes to different CSRs and 64-bit SRAM words must be serialised, * since interleaved access can result in lost writes. We use * efx_nic::biu_lock for this. * * We also serialise reads from 128-bit CSRs and SRAM with the same * spinlock. This may not be necessary, but it doesn't really matter * as there are no such reads on the fast path. * * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are * 128-bit but are special-cased in the BIU to avoid the need for * locking in the host: * * - They are write-only. * - The semantics of writing to these registers are such that * replacing the low 96 bits with zero does not affect functionality. * - If the host writes to the last dword address of such a register * (i.e. the high 32 bits) the underlying register will always be * written. If the collector and the current write together do not * provide values for all 128 bits of the register, the low 96 bits * will be written as zero. * - If the host writes to the address of any other part of such a * register while the collector already holds values for some other * register, the write is discarded and the collector maintains its * current state. * * The EF10 architecture exposes very few registers to the host and * most of them are only 32 bits wide. The only exceptions are the MC * doorbell register pair, which has its own latching, and * TX_DESC_UPD, which works in a similar way to the Falcon * architecture. */ #if BITS_PER_LONG == 64 #define EFX_USE_QWORD_IO … #endif /* Hardware issue requires that only 64-bit naturally aligned writes * are seen by hardware. Its not strictly necessary to restrict to * x86_64 arch, but done for safety since unusual write combining behaviour * can break PIO. */ #ifdef CONFIG_X86_64 /* PIO is a win only if write-combining is possible */ #ifdef ioremap_wc #define EFX_USE_PIO … #endif #endif static inline u32 efx_reg(struct efx_nic *efx, unsigned int reg) { … } #ifdef EFX_USE_QWORD_IO static inline void _efx_writeq(struct efx_nic *efx, __le64 value, unsigned int reg) { … } static inline __le64 _efx_readq(struct efx_nic *efx, unsigned int reg) { … } #endif static inline void _efx_writed(struct efx_nic *efx, __le32 value, unsigned int reg) { … } static inline __le32 _efx_readd(struct efx_nic *efx, unsigned int reg) { … } /* Write a normal 128-bit CSR, locking as appropriate. */ static inline void efx_writeo(struct efx_nic *efx, const efx_oword_t *value, unsigned int reg) { … } /* Write 64-bit SRAM through the supplied mapping, locking as appropriate. */ static inline void efx_sram_writeq(struct efx_nic *efx, void __iomem *membase, const efx_qword_t *value, unsigned int index) { … } /* Write a 32-bit CSR or the last dword of a special 128-bit CSR */ static inline void efx_writed(struct efx_nic *efx, const efx_dword_t *value, unsigned int reg) { … } /* Read a 128-bit CSR, locking as appropriate. */ static inline void efx_reado(struct efx_nic *efx, efx_oword_t *value, unsigned int reg) { … } /* Read 64-bit SRAM through the supplied mapping, locking as appropriate. */ static inline void efx_sram_readq(struct efx_nic *efx, void __iomem *membase, efx_qword_t *value, unsigned int index) { … } /* Read a 32-bit CSR or SRAM */ static inline void efx_readd(struct efx_nic *efx, efx_dword_t *value, unsigned int reg) { … } /* Write a 128-bit CSR forming part of a table */ static inline void efx_writeo_table(struct efx_nic *efx, const efx_oword_t *value, unsigned int reg, unsigned int index) { … } /* Read a 128-bit CSR forming part of a table */ static inline void efx_reado_table(struct efx_nic *efx, efx_oword_t *value, unsigned int reg, unsigned int index) { … } /* default VI stride (step between per-VI registers) is 8K on EF10 and * 64K on EF100 */ #define EFX_DEFAULT_VI_STRIDE … #define EF100_DEFAULT_VI_STRIDE … /* Calculate offset to page-mapped register */ static inline unsigned int efx_paged_reg(struct efx_nic *efx, unsigned int page, unsigned int reg) { … } /* Write the whole of RX_DESC_UPD or TX_DESC_UPD */ static inline void _efx_writeo_page(struct efx_nic *efx, efx_oword_t *value, unsigned int reg, unsigned int page) { … } #define efx_writeo_page(efx, value, reg, page) … /* Write a page-mapped 32-bit CSR (EVQ_RPTR, EVQ_TMR (EF10), or the * high bits of RX_DESC_UPD or TX_DESC_UPD) */ static inline void _efx_writed_page(struct efx_nic *efx, const efx_dword_t *value, unsigned int reg, unsigned int page) { … } #define efx_writed_page(efx, value, reg, page) … /* Write TIMER_COMMAND. This is a page-mapped 32-bit CSR, but a bug * in the BIU means that writes to TIMER_COMMAND[0] invalidate the * collector register. */ static inline void _efx_writed_page_locked(struct efx_nic *efx, const efx_dword_t *value, unsigned int reg, unsigned int page) { … } #define efx_writed_page_locked(efx, value, reg, page) … #endif /* EFX_IO_H */
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