/* SPDX-License-Identifier: GPL-2.0-only */ /**************************************************************************** * Driver for Solarflare network controllers and boards * Copyright 2005-2006 Fen Systems Ltd. * Copyright 2006-2013 Solarflare Communications Inc. * Copyright 2019-2020 Xilinx Inc. */ #ifndef EFX_NIC_COMMON_H #define EFX_NIC_COMMON_H #include "net_driver.h" #include "efx_common.h" #include "mcdi.h" #include "ptp.h" enum { … }; static inline int efx_nic_rev(struct efx_nic *efx) { … } /* Read the current event from the event queue */ static inline efx_qword_t *efx_event(struct efx_channel *channel, unsigned int index) { … } /* See if an event is present * * We check both the high and low dword of the event for all ones. We * wrote all ones when we cleared the event, and no valid event can * have all ones in either its high or low dwords. This approach is * robust against reordering. * * Note that using a single 64-bit comparison is incorrect; even * though the CPU read will be atomic, the DMA write may not be. */ static inline int efx_event_present(efx_qword_t *event) { … } /* Returns a pointer to the specified transmit descriptor in the TX * descriptor queue belonging to the specified channel. */ static inline efx_qword_t * efx_tx_desc(struct efx_tx_queue *tx_queue, unsigned int index) { … } /* Report whether this TX queue would be empty for the given write_count. * May return false negative. */ static inline bool efx_nic_tx_is_empty(struct efx_tx_queue *tx_queue, unsigned int write_count) { … } int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue, struct sk_buff *skb, bool *data_mapped); /* Decide whether to push a TX descriptor to the NIC vs merely writing * the doorbell. This can reduce latency when we are adding a single * descriptor to an empty queue, but is otherwise pointless. * We use the write_count used for the last doorbell push, to get the * NIC's view of the tx queue. */ static inline bool efx_nic_may_push_tx_desc(struct efx_tx_queue *tx_queue, unsigned int write_count) { … } /* Returns a pointer to the specified descriptor in the RX descriptor queue */ static inline efx_qword_t * efx_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index) { … } /* Alignment of PCIe DMA boundaries (4KB) */ #define EFX_PAGE_SIZE … /* Size and alignment of buffer table entries (same) */ #define EFX_BUF_SIZE … /* NIC-generic software stats */ enum { … }; #define EFX_GENERIC_SW_STAT(ext_name) … /* TX data path */ static inline int efx_nic_probe_tx(struct efx_tx_queue *tx_queue) { … } static inline void efx_nic_init_tx(struct efx_tx_queue *tx_queue) { … } static inline void efx_nic_remove_tx(struct efx_tx_queue *tx_queue) { … } static inline void efx_nic_push_buffers(struct efx_tx_queue *tx_queue) { … } /* RX data path */ static inline int efx_nic_probe_rx(struct efx_rx_queue *rx_queue) { … } static inline void efx_nic_init_rx(struct efx_rx_queue *rx_queue) { … } static inline void efx_nic_remove_rx(struct efx_rx_queue *rx_queue) { … } static inline void efx_nic_notify_rx_desc(struct efx_rx_queue *rx_queue) { … } static inline void efx_nic_generate_fill_event(struct efx_rx_queue *rx_queue) { … } /* Event data path */ static inline int efx_nic_probe_eventq(struct efx_channel *channel) { … } static inline int efx_nic_init_eventq(struct efx_channel *channel) { … } static inline void efx_nic_fini_eventq(struct efx_channel *channel) { … } static inline void efx_nic_remove_eventq(struct efx_channel *channel) { … } static inline int efx_nic_process_eventq(struct efx_channel *channel, int quota) { … } static inline void efx_nic_eventq_read_ack(struct efx_channel *channel) { … } void efx_nic_event_test_start(struct efx_channel *channel); bool efx_nic_event_present(struct efx_channel *channel); static inline void efx_sensor_event(struct efx_nic *efx, efx_qword_t *ev) { … } static inline unsigned int efx_rx_recycle_ring_size(const struct efx_nic *efx) { … } /* Some statistics are computed as A - B where A and B each increase * linearly with some hardware counter(s) and the counters are read * asynchronously. If the counters contributing to B are always read * after those contributing to A, the computed value may be lower than * the true value by some variable amount, and may decrease between * subsequent computations. * * We should never allow statistics to decrease or to exceed the true * value. Since the computed value will never be greater than the * true value, we can achieve this by only storing the computed value * when it increases. */ static inline void efx_update_diff_stat(u64 *stat, u64 diff) { … } /* Interrupts */ int efx_nic_init_interrupt(struct efx_nic *efx); int efx_nic_irq_test_start(struct efx_nic *efx); void efx_nic_fini_interrupt(struct efx_nic *efx); static inline int efx_nic_event_test_irq_cpu(struct efx_channel *channel) { … } static inline int efx_nic_irq_test_irq_cpu(struct efx_nic *efx) { … } /* Global Resources */ int efx_nic_alloc_buffer(struct efx_nic *efx, struct efx_buffer *buffer, unsigned int len, gfp_t gfp_flags); void efx_nic_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer); size_t efx_nic_get_regs_len(struct efx_nic *efx); void efx_nic_get_regs(struct efx_nic *efx, void *buf); #define EFX_MC_STATS_GENERATION_INVALID … size_t efx_nic_describe_stats(const struct efx_hw_stat_desc *desc, size_t count, const unsigned long *mask, u8 *names); int efx_nic_copy_stats(struct efx_nic *efx, __le64 *dest); void efx_nic_update_stats(const struct efx_hw_stat_desc *desc, size_t count, const unsigned long *mask, u64 *stats, const void *dma_buf, bool accumulate); void efx_nic_fix_nodesc_drop_stat(struct efx_nic *efx, u64 *stat); static inline size_t efx_nic_update_stats_atomic(struct efx_nic *efx, u64 *full_stats, struct rtnl_link_stats64 *core_stats) { … } #define EFX_MAX_FLUSH_TIME … #endif /* EFX_NIC_COMMON_H */
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