/* SPDX-License-Identifier: GPL-2.0-only */ /******************************************************************************* Header file for stmmac platform data Copyright (C) 2009 STMicroelectronics Ltd Author: Giuseppe Cavallaro <[email protected]> *******************************************************************************/ #ifndef __STMMAC_PLATFORM_DATA #define __STMMAC_PLATFORM_DATA #include <linux/platform_device.h> #include <linux/phylink.h> #define MTL_MAX_RX_QUEUES … #define MTL_MAX_TX_QUEUES … #define STMMAC_CH_MAX … #define STMMAC_RX_COE_NONE … #define STMMAC_RX_COE_TYPE1 … #define STMMAC_RX_COE_TYPE2 … /* Define the macros for CSR clock range parameters to be passed by * platform code. * This could also be configured at run time using CPU freq framework. */ /* MDC Clock Selection define*/ #define STMMAC_CSR_60_100M … #define STMMAC_CSR_100_150M … #define STMMAC_CSR_20_35M … #define STMMAC_CSR_35_60M … #define STMMAC_CSR_150_250M … #define STMMAC_CSR_250_300M … /* MTL algorithms identifiers */ #define MTL_TX_ALGORITHM_WRR … #define MTL_TX_ALGORITHM_WFQ … #define MTL_TX_ALGORITHM_DWRR … #define MTL_TX_ALGORITHM_SP … #define MTL_RX_ALGORITHM_SP … #define MTL_RX_ALGORITHM_WSP … /* RX/TX Queue Mode */ #define MTL_QUEUE_AVB … #define MTL_QUEUE_DCB … /* The MDC clock could be set higher than the IEEE 802.3 * specified frequency limit 0f 2.5 MHz, by programming a clock divider * of value different than the above defined values. The resultant MDIO * clock frequency of 12.5 MHz is applicable for the interfacing chips * supporting higher MDC clocks. * The MDC clock selection macros need to be defined for MDC clock rate * of 12.5 MHz, corresponding to the following selection. */ #define STMMAC_CSR_I_4 … #define STMMAC_CSR_I_6 … #define STMMAC_CSR_I_8 … #define STMMAC_CSR_I_10 … #define STMMAC_CSR_I_12 … #define STMMAC_CSR_I_14 … #define STMMAC_CSR_I_16 … #define STMMAC_CSR_I_18 … /* AXI DMA Burst length supported */ #define DMA_AXI_BLEN_4 … #define DMA_AXI_BLEN_8 … #define DMA_AXI_BLEN_16 … #define DMA_AXI_BLEN_32 … #define DMA_AXI_BLEN_64 … #define DMA_AXI_BLEN_128 … #define DMA_AXI_BLEN_256 … #define DMA_AXI_BLEN_ALL … struct stmmac_priv; /* Platfrom data for platform device structure's platform_data field */ struct stmmac_mdio_bus_data { … }; struct stmmac_dma_cfg { … }; #define AXI_BLEN … struct stmmac_axi { … }; struct stmmac_rxq_cfg { … }; struct stmmac_txq_cfg { … }; struct stmmac_safety_feature_cfg { … }; /* Addresses that may be customized by a platform */ struct dwmac4_addrs { … }; #define STMMAC_FLAG_HAS_INTEGRATED_PCS … #define STMMAC_FLAG_SPH_DISABLE … #define STMMAC_FLAG_USE_PHY_WOL … #define STMMAC_FLAG_HAS_SUN8I … #define STMMAC_FLAG_TSO_EN … #define STMMAC_FLAG_SERDES_UP_AFTER_PHY_LINKUP … #define STMMAC_FLAG_VLAN_FAIL_Q_EN … #define STMMAC_FLAG_MULTI_MSI_EN … #define STMMAC_FLAG_EXT_SNAPSHOT_EN … #define STMMAC_FLAG_INT_SNAPSHOT_EN … #define STMMAC_FLAG_RX_CLK_RUNS_IN_LPI … #define STMMAC_FLAG_EN_TX_LPI_CLOCKGATING … #define STMMAC_FLAG_HWTSTAMP_CORRECT_LATENCY … struct plat_stmmacenet_data { … }; #endif
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