// SPDX-License-Identifier: GPL-2.0 /* * Texas Instruments CPDMA Driver * * Copyright (C) 2010 Texas Instruments * */ #include <linux/kernel.h> #include <linux/spinlock.h> #include <linux/device.h> #include <linux/module.h> #include <linux/slab.h> #include <linux/err.h> #include <linux/dma-mapping.h> #include <linux/io.h> #include <linux/delay.h> #include <linux/genalloc.h> #include "davinci_cpdma.h" /* DMA Registers */ #define CPDMA_TXIDVER … #define CPDMA_TXCONTROL … #define CPDMA_TXTEARDOWN … #define CPDMA_RXIDVER … #define CPDMA_RXCONTROL … #define CPDMA_SOFTRESET … #define CPDMA_RXTEARDOWN … #define CPDMA_TX_PRI0_RATE … #define CPDMA_TXINTSTATRAW … #define CPDMA_TXINTSTATMASKED … #define CPDMA_TXINTMASKSET … #define CPDMA_TXINTMASKCLEAR … #define CPDMA_MACINVECTOR … #define CPDMA_MACEOIVECTOR … #define CPDMA_RXINTSTATRAW … #define CPDMA_RXINTSTATMASKED … #define CPDMA_RXINTMASKSET … #define CPDMA_RXINTMASKCLEAR … #define CPDMA_DMAINTSTATRAW … #define CPDMA_DMAINTSTATMASKED … #define CPDMA_DMAINTMASKSET … #define CPDMA_DMAINTMASKCLEAR … #define CPDMA_DMAINT_HOSTERR … /* the following exist only if has_ext_regs is set */ #define CPDMA_DMACONTROL … #define CPDMA_DMASTATUS … #define CPDMA_RXBUFFOFS … #define CPDMA_EM_CONTROL … /* Descriptor mode bits */ #define CPDMA_DESC_SOP … #define CPDMA_DESC_EOP … #define CPDMA_DESC_OWNER … #define CPDMA_DESC_EOQ … #define CPDMA_DESC_TD_COMPLETE … #define CPDMA_DESC_PASS_CRC … #define CPDMA_DESC_TO_PORT_EN … #define CPDMA_TO_PORT_SHIFT … #define CPDMA_DESC_PORT_MASK … #define CPDMA_DESC_CRC_LEN … #define CPDMA_TEARDOWN_VALUE … #define CPDMA_MAX_RLIM_CNT … struct cpdma_desc { … }; struct cpdma_desc_pool { … }; enum cpdma_state { … }; struct cpdma_ctlr { … }; struct cpdma_chan { … }; struct cpdma_control_info { … }; struct submit_info { … }; static struct cpdma_control_info controls[] = …; #define tx_chan_num(chan) … #define rx_chan_num(chan) … #define is_rx_chan(chan) … #define is_tx_chan(chan) … #define __chan_linear(chan_num) … #define chan_linear(chan) … /* The following make access to common cpdma_ctlr params more readable */ #define dmaregs … #define num_chan … /* various accessors */ #define dma_reg_read(ctlr, ofs) … #define chan_read(chan, fld) … #define desc_read(desc, fld) … #define dma_reg_write(ctlr, ofs, v) … #define chan_write(chan, fld, v) … #define desc_write(desc, fld, v) … #define cpdma_desc_to_port(chan, mode, directed) … #define CPDMA_DMA_EXT_MAP … static void cpdma_desc_pool_destroy(struct cpdma_ctlr *ctlr) { … } /* * Utility constructs for a cpdma descriptor pool. Some devices (e.g. davinci * emac) have dedicated on-chip memory for these descriptors. Some other * devices (e.g. cpsw switches) use plain old memory. Descriptor pools * abstract out these details */ static int cpdma_desc_pool_create(struct cpdma_ctlr *ctlr) { … } static inline dma_addr_t desc_phys(struct cpdma_desc_pool *pool, struct cpdma_desc __iomem *desc) { … } static inline struct cpdma_desc __iomem * desc_from_phys(struct cpdma_desc_pool *pool, dma_addr_t dma) { … } static struct cpdma_desc __iomem * cpdma_desc_alloc(struct cpdma_desc_pool *pool) { … } static void cpdma_desc_free(struct cpdma_desc_pool *pool, struct cpdma_desc __iomem *desc, int num_desc) { … } static int _cpdma_control_set(struct cpdma_ctlr *ctlr, int control, int value) { … } static int _cpdma_control_get(struct cpdma_ctlr *ctlr, int control) { … } /* cpdma_chan_set_chan_shaper - set shaper for a channel * Has to be called under ctlr lock */ static int cpdma_chan_set_chan_shaper(struct cpdma_chan *chan) { … } static int cpdma_chan_on(struct cpdma_chan *chan) { … } /* cpdma_chan_fit_rate - set rate for a channel and check if it's possible. * rmask - mask of rate limited channels * Returns min rate in Kb/s */ static int cpdma_chan_fit_rate(struct cpdma_chan *ch, u32 rate, u32 *rmask, int *prio_mode) { … } static u32 cpdma_chan_set_factors(struct cpdma_ctlr *ctlr, struct cpdma_chan *ch) { … } struct cpdma_ctlr *cpdma_ctlr_create(struct cpdma_params *params) { … } int cpdma_ctlr_start(struct cpdma_ctlr *ctlr) { … } int cpdma_ctlr_stop(struct cpdma_ctlr *ctlr) { … } int cpdma_ctlr_destroy(struct cpdma_ctlr *ctlr) { … } int cpdma_ctlr_int_ctrl(struct cpdma_ctlr *ctlr, bool enable) { … } void cpdma_ctlr_eoi(struct cpdma_ctlr *ctlr, u32 value) { … } u32 cpdma_ctrl_rxchs_state(struct cpdma_ctlr *ctlr) { … } u32 cpdma_ctrl_txchs_state(struct cpdma_ctlr *ctlr) { … } static void cpdma_chan_set_descs(struct cpdma_ctlr *ctlr, int rx, int desc_num, int per_ch_desc) { … } /* * cpdma_chan_split_pool - Splits ctrl pool between all channels. * Has to be called under ctlr lock */ static int cpdma_chan_split_pool(struct cpdma_ctlr *ctlr) { … } /* cpdma_chan_set_weight - set weight of a channel in percentage. * Tx and Rx channels have separate weights. That is 100% for RX * and 100% for Tx. The weight is used to split cpdma resources * in correct proportion required by the channels, including number * of descriptors. The channel rate is not enough to know the * weight of a channel as the maximum rate of an interface is needed. * If weight = 0, then channel uses rest of descriptors leaved by * weighted channels. */ int cpdma_chan_set_weight(struct cpdma_chan *ch, int weight) { … } /* cpdma_chan_get_min_rate - get minimum allowed rate for channel * Should be called before cpdma_chan_set_rate. * Returns min rate in Kb/s */ u32 cpdma_chan_get_min_rate(struct cpdma_ctlr *ctlr) { … } /* cpdma_chan_set_rate - limits bandwidth for transmit channel. * The bandwidth * limited channels have to be in order beginning from lowest. * ch - transmit channel the bandwidth is configured for * rate - bandwidth in Kb/s, if 0 - then off shaper */ int cpdma_chan_set_rate(struct cpdma_chan *ch, u32 rate) { … } u32 cpdma_chan_get_rate(struct cpdma_chan *ch) { … } struct cpdma_chan *cpdma_chan_create(struct cpdma_ctlr *ctlr, int chan_num, cpdma_handler_fn handler, int rx_type) { … } int cpdma_chan_get_rx_buf_num(struct cpdma_chan *chan) { … } int cpdma_chan_destroy(struct cpdma_chan *chan) { … } int cpdma_chan_get_stats(struct cpdma_chan *chan, struct cpdma_chan_stats *stats) { … } static void __cpdma_chan_submit(struct cpdma_chan *chan, struct cpdma_desc __iomem *desc) { … } static int cpdma_chan_submit_si(struct submit_info *si) { … } int cpdma_chan_idle_submit(struct cpdma_chan *chan, void *token, void *data, int len, int directed) { … } int cpdma_chan_idle_submit_mapped(struct cpdma_chan *chan, void *token, dma_addr_t data, int len, int directed) { … } int cpdma_chan_submit(struct cpdma_chan *chan, void *token, void *data, int len, int directed) { … } int cpdma_chan_submit_mapped(struct cpdma_chan *chan, void *token, dma_addr_t data, int len, int directed) { … } bool cpdma_check_free_tx_desc(struct cpdma_chan *chan) { … } static void __cpdma_chan_free(struct cpdma_chan *chan, struct cpdma_desc __iomem *desc, int outlen, int status) { … } static int __cpdma_chan_process(struct cpdma_chan *chan) { … } int cpdma_chan_process(struct cpdma_chan *chan, int quota) { … } int cpdma_chan_start(struct cpdma_chan *chan) { … } int cpdma_chan_stop(struct cpdma_chan *chan) { … } int cpdma_chan_int_ctrl(struct cpdma_chan *chan, bool enable) { … } int cpdma_control_get(struct cpdma_ctlr *ctlr, int control) { … } int cpdma_control_set(struct cpdma_ctlr *ctlr, int control, int value) { … } int cpdma_get_num_rx_descs(struct cpdma_ctlr *ctlr) { … } int cpdma_get_num_tx_descs(struct cpdma_ctlr *ctlr) { … } int cpdma_set_num_rx_descs(struct cpdma_ctlr *ctlr, int num_rx_desc) { … }
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