/* SPDX-License-Identifier: GPL-2.0 */ /* * Texas Instruments Ethernet Switch Driver */ #ifndef DRIVERS_NET_ETHERNET_TI_CPSW_PRIV_H_ #define DRIVERS_NET_ETHERNET_TI_CPSW_PRIV_H_ #include <net/xdp.h> #include <uapi/linux/bpf.h> #include "davinci_cpdma.h" #define CPSW_DEBUG … #define cpsw_info(priv, type, format, ...) … #define cpsw_err(priv, type, format, ...) … #define cpsw_dbg(priv, type, format, ...) … #define cpsw_notice(priv, type, format, ...) … #define ALE_ALL_PORTS … #define CPSW_MAJOR_VERSION(reg) … #define CPSW_MINOR_VERSION(reg) … #define CPSW_RTL_VERSION(reg) … #define CPSW_VERSION_1 … #define CPSW_VERSION_2 … #define CPSW_VERSION_3 … #define CPSW_VERSION_4 … #define HOST_PORT_NUM … #define CPSW_ALE_PORTS_NUM … #define CPSW_SLAVE_PORTS_NUM … #define SLIVER_SIZE … #define CPSW1_HOST_PORT_OFFSET … #define CPSW1_SLAVE_OFFSET … #define CPSW1_SLAVE_SIZE … #define CPSW1_CPDMA_OFFSET … #define CPSW1_STATERAM_OFFSET … #define CPSW1_HW_STATS … #define CPSW1_CPTS_OFFSET … #define CPSW1_ALE_OFFSET … #define CPSW1_SLIVER_OFFSET … #define CPSW1_WR_OFFSET … #define CPSW2_HOST_PORT_OFFSET … #define CPSW2_SLAVE_OFFSET … #define CPSW2_SLAVE_SIZE … #define CPSW2_CPDMA_OFFSET … #define CPSW2_HW_STATS … #define CPSW2_STATERAM_OFFSET … #define CPSW2_CPTS_OFFSET … #define CPSW2_ALE_OFFSET … #define CPSW2_SLIVER_OFFSET … #define CPSW2_BD_OFFSET … #define CPSW2_WR_OFFSET … #define CPDMA_RXTHRESH … #define CPDMA_RXFREE … #define CPDMA_TXHDP … #define CPDMA_RXHDP … #define CPDMA_TXCP … #define CPDMA_RXCP … #define CPSW_RX_VLAN_ENCAP_HDR_SIZE … #define CPSW_MIN_PACKET_SIZE_VLAN … #define CPSW_MIN_PACKET_SIZE … #define CPSW_MAX_PACKET_SIZE … #define RX_PRIORITY_MAPPING … #define TX_PRIORITY_MAPPING … #define CPDMA_TX_PRIORITY_MAP … #define CPSW_VLAN_AWARE … #define CPSW_RX_VLAN_ENCAP … #define CPSW_ALE_VLAN_AWARE … #define CPSW_FIFO_NORMAL_MODE … #define CPSW_FIFO_DUAL_MAC_MODE … #define CPSW_FIFO_RATE_LIMIT_MODE … #define CPSW_INTPACEEN … #define CPSW_INTPRESCALE_MASK … #define CPSW_CMINTMAX_CNT … #define CPSW_CMINTMIN_CNT … #define CPSW_CMINTMAX_INTVL … #define CPSW_CMINTMIN_INTVL … #define IRQ_NUM … #define CPSW_MAX_QUEUES … #define CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT … #define CPSW_ALE_AGEOUT_DEFAULT … #define CPSW_FIFO_QUEUE_TYPE_SHIFT … #define CPSW_FIFO_SHAPE_EN_SHIFT … #define CPSW_FIFO_RATE_EN_SHIFT … #define CPSW_TC_NUM … #define CPSW_FIFO_SHAPERS_NUM … #define CPSW_PCT_MASK … #define CPSW_BD_RAM_SIZE … #define CPSW_RX_VLAN_ENCAP_HDR_PRIO_SHIFT … #define CPSW_RX_VLAN_ENCAP_HDR_PRIO_MSK … #define CPSW_RX_VLAN_ENCAP_HDR_VID_SHIFT … #define CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_SHIFT … #define CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_MSK … enum { … }; struct cpsw_wr_regs { … }; struct cpsw_ss_regs { … }; /* CPSW_PORT_V1 */ #define CPSW1_MAX_BLKS … #define CPSW1_BLK_CNT … #define CPSW1_TX_IN_CTL … #define CPSW1_PORT_VLAN … #define CPSW1_TX_PRI_MAP … #define CPSW1_TS_CTL … #define CPSW1_TS_SEQ_LTYPE … #define CPSW1_TS_VLAN … /* CPSW_PORT_V2 */ #define CPSW2_CONTROL … #define CPSW2_MAX_BLKS … #define CPSW2_BLK_CNT … #define CPSW2_TX_IN_CTL … #define CPSW2_PORT_VLAN … #define CPSW2_TX_PRI_MAP … #define CPSW2_TS_SEQ_MTYPE … /* CPSW_PORT_V1 and V2 */ #define SA_LO … #define SA_HI … #define SEND_PERCENT … /* CPSW_PORT_V2 only */ #define RX_DSCP_PRI_MAP0 … #define RX_DSCP_PRI_MAP1 … #define RX_DSCP_PRI_MAP2 … #define RX_DSCP_PRI_MAP3 … #define RX_DSCP_PRI_MAP4 … #define RX_DSCP_PRI_MAP5 … #define RX_DSCP_PRI_MAP6 … #define RX_DSCP_PRI_MAP7 … /* Bit definitions for the CPSW2_CONTROL register */ #define PASS_PRI_TAGGED … #define VLAN_LTYPE2_EN … #define VLAN_LTYPE1_EN … #define DSCP_PRI_EN … #define TS_107 … #define TS_320 … #define TS_319 … #define TS_132 … #define TS_131 … #define TS_130 … #define TS_129 … #define TS_TTL_NONZERO … #define TS_ANNEX_F_EN … #define TS_ANNEX_D_EN … #define TS_LTYPE2_EN … #define TS_LTYPE1_EN … #define TS_TX_EN … #define TS_RX_EN … #define CTRL_V2_TS_BITS … #define CTRL_V2_ALL_TS_MASK … #define CTRL_V2_TX_TS_BITS … #define CTRL_V2_RX_TS_BITS … #define CTRL_V3_TS_BITS … #define CTRL_V3_ALL_TS_MASK … #define CTRL_V3_TX_TS_BITS … #define CTRL_V3_RX_TS_BITS … /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */ #define TS_SEQ_ID_OFFSET_SHIFT … #define TS_SEQ_ID_OFFSET_MASK … #define TS_MSG_TYPE_EN_SHIFT … #define TS_MSG_TYPE_EN_MASK … /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ #define EVENT_MSG_BITS … /* Bit definitions for the CPSW1_TS_CTL register */ #define CPSW_V1_TS_RX_EN … #define CPSW_V1_TS_TX_EN … #define CPSW_V1_MSG_TYPE_OFS … /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */ #define CPSW_V1_SEQ_ID_OFS_SHIFT … #define CPSW_MAX_BLKS_TX … #define CPSW_MAX_BLKS_TX_SHIFT … #define CPSW_MAX_BLKS_RX … struct cpsw_host_regs { … }; struct cpsw_slave_data { … }; struct cpsw_platform_data { … }; struct cpsw_slave { … }; static inline u32 slave_read(struct cpsw_slave *slave, u32 offset) { … } static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset) { … } struct cpsw_vector { … }; struct cpsw_common { … }; struct cpsw_ale_ratelimit { … }; struct cpsw_priv { … }; #define ndev_to_cpsw(ndev) … #define napi_to_cpsw(napi) … extern int (*cpsw_slave_index)(struct cpsw_common *cpsw, struct cpsw_priv *priv); struct addr_sync_ctx { … }; #define CPSW_XMETA_OFFSET … #define CPSW_XDP_CONSUMED … #define CPSW_XDP_PASS … struct __aligned(sizeof(long)) cpsw_meta_xdp { … }; /* The buf includes headroom compatible with both skb and xdpf */ #define CPSW_HEADROOM_NA … static inline int cpsw_is_xdpf_handle(void *handle) { … } static inline void *cpsw_xdpf_to_handle(struct xdp_frame *xdpf) { … } static inline struct xdp_frame *cpsw_handle_to_xdpf(void *handle) { … } int cpsw_init_common(struct cpsw_common *cpsw, void __iomem *ss_regs, int ale_ageout, phys_addr_t desc_mem_phys, int descs_pool_size); void cpsw_split_res(struct cpsw_common *cpsw); int cpsw_fill_rx_channels(struct cpsw_priv *priv); void cpsw_intr_enable(struct cpsw_common *cpsw); void cpsw_intr_disable(struct cpsw_common *cpsw); void cpsw_tx_handler(void *token, int len, int status); int cpsw_create_xdp_rxqs(struct cpsw_common *cpsw); void cpsw_destroy_xdp_rxqs(struct cpsw_common *cpsw); int cpsw_ndo_bpf(struct net_device *ndev, struct netdev_bpf *bpf); int cpsw_xdp_tx_frame(struct cpsw_priv *priv, struct xdp_frame *xdpf, struct page *page, int port); int cpsw_run_xdp(struct cpsw_priv *priv, int ch, struct xdp_buff *xdp, struct page *page, int port, int *len); irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id); irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id); irqreturn_t cpsw_misc_interrupt(int irq, void *dev_id); int cpsw_tx_mq_poll(struct napi_struct *napi_tx, int budget); int cpsw_tx_poll(struct napi_struct *napi_tx, int budget); int cpsw_rx_mq_poll(struct napi_struct *napi_rx, int budget); int cpsw_rx_poll(struct napi_struct *napi_rx, int budget); void cpsw_rx_vlan_encap(struct sk_buff *skb); void soft_reset(const char *module, void __iomem *reg); void cpsw_set_slave_mac(struct cpsw_slave *slave, struct cpsw_priv *priv); void cpsw_ndo_tx_timeout(struct net_device *ndev, unsigned int txqueue); int cpsw_need_resplit(struct cpsw_common *cpsw); int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd); int cpsw_ndo_set_tx_maxrate(struct net_device *ndev, int queue, u32 rate); int cpsw_ndo_setup_tc(struct net_device *ndev, enum tc_setup_type type, void *type_data); bool cpsw_shp_is_off(struct cpsw_priv *priv); void cpsw_cbs_resume(struct cpsw_slave *slave, struct cpsw_priv *priv); void cpsw_mqprio_resume(struct cpsw_slave *slave, struct cpsw_priv *priv); void cpsw_qos_clsflower_resume(struct cpsw_priv *priv); /* ethtool */ u32 cpsw_get_msglevel(struct net_device *ndev); void cpsw_set_msglevel(struct net_device *ndev, u32 value); int cpsw_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *coal, struct kernel_ethtool_coalesce *kernel_coal, struct netlink_ext_ack *extack); int cpsw_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *coal, struct kernel_ethtool_coalesce *kernel_coal, struct netlink_ext_ack *extack); int cpsw_get_sset_count(struct net_device *ndev, int sset); void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data); void cpsw_get_ethtool_stats(struct net_device *ndev, struct ethtool_stats *stats, u64 *data); void cpsw_get_pauseparam(struct net_device *ndev, struct ethtool_pauseparam *pause); void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol); int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol); int cpsw_get_regs_len(struct net_device *ndev); void cpsw_get_regs(struct net_device *ndev, struct ethtool_regs *regs, void *p); int cpsw_ethtool_op_begin(struct net_device *ndev); void cpsw_ethtool_op_complete(struct net_device *ndev); void cpsw_get_channels(struct net_device *ndev, struct ethtool_channels *ch); int cpsw_get_link_ksettings(struct net_device *ndev, struct ethtool_link_ksettings *ecmd); int cpsw_set_link_ksettings(struct net_device *ndev, const struct ethtool_link_ksettings *ecmd); int cpsw_get_eee(struct net_device *ndev, struct ethtool_keee *edata); int cpsw_set_eee(struct net_device *ndev, struct ethtool_keee *edata); int cpsw_nway_reset(struct net_device *ndev); void cpsw_get_ringparam(struct net_device *ndev, struct ethtool_ringparam *ering, struct kernel_ethtool_ringparam *kernel_ering, struct netlink_ext_ack *extack); int cpsw_set_ringparam(struct net_device *ndev, struct ethtool_ringparam *ering, struct kernel_ethtool_ringparam *kernel_ering, struct netlink_ext_ack *extack); int cpsw_set_channels_common(struct net_device *ndev, struct ethtool_channels *chs, cpdma_handler_fn rx_handler); int cpsw_get_ts_info(struct net_device *ndev, struct kernel_ethtool_ts_info *info); #endif /* DRIVERS_NET_ETHERNET_TI_CPSW_PRIV_H_ */
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