/* SPDX-License-Identifier: GPL-2.0 */ /* Copyright (c) 2015 - 2022 Beijing WangXun Technology Co., Ltd. */ #ifndef _WX_TYPE_H_ #define _WX_TYPE_H_ #include <linux/bitfield.h> #include <linux/netdevice.h> #include <linux/if_vlan.h> #include <linux/phylink.h> #include <net/ip.h> #define WX_NCSI_SUP … #define WX_NCSI_MASK … #define WX_WOL_SUP … #define WX_WOL_MASK … /* MSI-X capability fields masks */ #define WX_PCIE_MSIX_TBL_SZ_MASK … #define WX_PCI_LINK_STATUS … /**************** Global Registers ****************************/ /* chip control Registers */ #define WX_MIS_PWR … #define WX_MIS_RST … #define WX_MIS_RST_LAN_RST(_i) … #define WX_MIS_RST_SW_RST … #define WX_MIS_ST … #define WX_MIS_ST_MNG_INIT_DN … #define WX_MIS_SWSM … #define WX_MIS_SWSM_SMBI … #define WX_MIS_RST_ST … #define WX_MIS_RST_ST_RST_INI_SHIFT … #define WX_MIS_RST_ST_RST_INIT … /* FMGR Registers */ #define WX_SPI_CMD … #define WX_SPI_CMD_READ_DWORD … #define WX_SPI_CLK_DIV … #define WX_SPI_CMD_CMD(_v) … #define WX_SPI_CMD_CLK(_v) … #define WX_SPI_CMD_ADDR(_v) … #define WX_SPI_DATA … #define WX_SPI_DATA_BYPASS … #define WX_SPI_DATA_OP_DONE … #define WX_SPI_STATUS … #define WX_SPI_STATUS_OPDONE … #define WX_SPI_STATUS_FLASH_BYPASS … #define WX_SPI_ILDR_STATUS … /* Sensors for PVT(Process Voltage Temperature) */ #define WX_TS_EN … #define WX_TS_EN_ENA … #define WX_TS_ALARM_THRE … #define WX_TS_DALARM_THRE … #define WX_TS_INT_EN … #define WX_TS_INT_EN_DALARM_INT_EN … #define WX_TS_INT_EN_ALARM_INT_EN … #define WX_TS_ALARM_ST … #define WX_TS_ALARM_ST_DALARM … #define WX_TS_ALARM_ST_ALARM … /* statistic */ #define WX_TX_FRAME_CNT_GOOD_BAD_L … #define WX_TX_BC_FRAMES_GOOD_L … #define WX_TX_MC_FRAMES_GOOD_L … #define WX_RX_FRAME_CNT_GOOD_BAD_L … #define WX_RX_BC_FRAMES_GOOD_L … #define WX_RX_MC_FRAMES_GOOD_L … #define WX_RX_CRC_ERROR_FRAMES_L … #define WX_RX_LEN_ERROR_FRAMES_L … #define WX_RX_UNDERSIZE_FRAMES_GOOD … #define WX_RX_OVERSIZE_FRAMES_GOOD … #define WX_MAC_LXONOFFRXC … /*********************** Receive DMA registers **************************/ #define WX_RDM_DRP_PKT … #define WX_RDM_PKT_CNT … #define WX_RDM_BYTE_CNT_LSB … #define WX_RDM_BMC2OS_CNT … /************************* Port Registers ************************************/ /* port cfg Registers */ #define WX_CFG_PORT_CTL … #define WX_CFG_PORT_CTL_DRV_LOAD … #define WX_CFG_PORT_CTL_QINQ … #define WX_CFG_PORT_CTL_D_VLAN … #define WX_CFG_TAG_TPID(_i) … #define WX_CFG_PORT_CTL_NUM_VT_MASK … /* GPIO Registers */ #define WX_GPIO_DR … #define WX_GPIO_DR_0 … #define WX_GPIO_DR_1 … #define WX_GPIO_DDR … #define WX_GPIO_DDR_0 … #define WX_GPIO_DDR_1 … #define WX_GPIO_CTL … #define WX_GPIO_INTEN … #define WX_GPIO_INTEN_0 … #define WX_GPIO_INTEN_1 … #define WX_GPIO_INTMASK … #define WX_GPIO_INTTYPE_LEVEL … #define WX_GPIO_POLARITY … #define WX_GPIO_INTSTATUS … #define WX_GPIO_EOI … #define WX_GPIO_EXT … /*********************** Transmit DMA registers **************************/ /* transmit global control */ #define WX_TDM_CTL … /* TDM CTL BIT */ #define WX_TDM_CTL_TE … #define WX_TDM_PB_THRE(_i) … #define WX_TDM_RP_IDX … #define WX_TDM_PKT_CNT … #define WX_TDM_BYTE_CNT_LSB … #define WX_TDM_OS2BMC_CNT … #define WX_TDM_RP_RATE … /***************************** RDB registers *********************************/ /* receive packet buffer */ #define WX_RDB_PB_CTL … #define WX_RDB_PB_CTL_RXEN … #define WX_RDB_PB_CTL_DISABLED … #define WX_RDB_PB_SZ(_i) … #define WX_RDB_PB_SZ_SHIFT … /* statistic */ #define WX_RDB_PFCMACDAL … #define WX_RDB_PFCMACDAH … #define WX_RDB_LXOFFTXC … #define WX_RDB_LXONTXC … /* Flow Control Registers */ #define WX_RDB_RFCV … #define WX_RDB_RFCL … #define WX_RDB_RFCL_XONE … #define WX_RDB_RFCH … #define WX_RDB_RFCH_XOFFE … #define WX_RDB_RFCRT … #define WX_RDB_RFCC … #define WX_RDB_RFCC_RFCE_802_3X … /* ring assignment */ #define WX_RDB_PL_CFG(_i) … #define WX_RDB_PL_CFG_L4HDR … #define WX_RDB_PL_CFG_L3HDR … #define WX_RDB_PL_CFG_L2HDR … #define WX_RDB_PL_CFG_TUN_TUNHDR … #define WX_RDB_PL_CFG_TUN_OUTL2HDR … #define WX_RDB_RSSTBL(_i) … #define WX_RDB_RSSRK(_i) … #define WX_RDB_RA_CTL … #define WX_RDB_RA_CTL_RSS_EN … #define WX_RDB_RA_CTL_RSS_IPV4_TCP … #define WX_RDB_RA_CTL_RSS_IPV4 … #define WX_RDB_RA_CTL_RSS_IPV6 … #define WX_RDB_RA_CTL_RSS_IPV6_TCP … #define WX_RDB_RA_CTL_RSS_IPV4_UDP … #define WX_RDB_RA_CTL_RSS_IPV6_UDP … #define WX_RDB_FDIR_MATCH … #define WX_RDB_FDIR_MISS … /******************************* PSR Registers *******************************/ /* psr control */ #define WX_PSR_CTL … /* Header split receive */ #define WX_PSR_CTL_SW_EN … #define WX_PSR_CTL_RSC_ACK … #define WX_PSR_CTL_RSC_DIS … #define WX_PSR_CTL_PCSD … #define WX_PSR_CTL_IPPCSE … #define WX_PSR_CTL_BAM … #define WX_PSR_CTL_UPE … #define WX_PSR_CTL_MPE … #define WX_PSR_CTL_MFE … #define WX_PSR_CTL_MO_SHIFT … #define WX_PSR_CTL_MO … #define WX_PSR_CTL_TPE … #define WX_PSR_MAX_SZ … #define WX_PSR_VLAN_CTL … #define WX_PSR_VLAN_CTL_CFIEN … #define WX_PSR_VLAN_CTL_VFE … /* mcasst/ucast overflow tbl */ #define WX_PSR_MC_TBL(_i) … #define WX_PSR_UC_TBL(_i) … /* VM L2 contorl */ #define WX_PSR_VM_L2CTL(_i) … #define WX_PSR_VM_L2CTL_UPE … #define WX_PSR_VM_L2CTL_VACC … #define WX_PSR_VM_L2CTL_AUPE … #define WX_PSR_VM_L2CTL_ROMPE … #define WX_PSR_VM_L2CTL_ROPE … #define WX_PSR_VM_L2CTL_BAM … #define WX_PSR_VM_L2CTL_MPE … /* Management */ #define WX_PSR_MNG_FLEX_SEL … #define WX_PSR_MNG_FLEX_DW_L(_i) … #define WX_PSR_MNG_FLEX_DW_H(_i) … #define WX_PSR_MNG_FLEX_MSK(_i) … #define WX_PSR_LAN_FLEX_SEL … #define WX_PSR_LAN_FLEX_DW_L(_i) … #define WX_PSR_LAN_FLEX_DW_H(_i) … #define WX_PSR_LAN_FLEX_MSK(_i) … #define WX_PSR_WKUP_CTL … /* Wake Up Filter Control Bit */ #define WX_PSR_WKUP_CTL_MAG … /* vlan tbl */ #define WX_PSR_VLAN_TBL(_i) … /* mac switcher */ #define WX_PSR_MAC_SWC_AD_L … #define WX_PSR_MAC_SWC_AD_H … #define WX_PSR_MAC_SWC_AD_H_AD(v) … #define WX_PSR_MAC_SWC_AD_H_ADTYPE(v) … #define WX_PSR_MAC_SWC_AD_H_AV … #define WX_PSR_MAC_SWC_VM_L … #define WX_PSR_MAC_SWC_VM_H … #define WX_PSR_MAC_SWC_IDX … #define WX_CLEAR_VMDQ_ALL … /* vlan switch */ #define WX_PSR_VLAN_SWC … #define WX_PSR_VLAN_SWC_VM_L … #define WX_PSR_VLAN_SWC_VM_H … #define WX_PSR_VLAN_SWC_IDX … /* VLAN pool filtering masks */ #define WX_PSR_VLAN_SWC_VIEN … #define WX_PSR_VLAN_SWC_ENTRIES … /********************************* RSEC **************************************/ /* general rsec */ #define WX_RSC_CTL … #define WX_RSC_CTL_SAVE_MAC_ERR … #define WX_RSC_CTL_CRC_STRIP … #define WX_RSC_CTL_RX_DIS … #define WX_RSC_ST … #define WX_RSC_ST_RSEC_RDY … /****************************** TDB ******************************************/ #define WX_TDB_PB_SZ(_i) … #define WX_TXPKT_SIZE_MAX … /****************************** TSEC *****************************************/ /* Security Control Registers */ #define WX_TSC_CTL … #define WX_TSC_CTL_TX_DIS … #define WX_TSC_CTL_TSEC_DIS … #define WX_TSC_ST … #define WX_TSC_ST_SECTX_RDY … #define WX_TSC_BUF_AE … #define WX_TSC_BUF_AE_THR … /************************************** MNG ********************************/ #define WX_MNG_SWFW_SYNC … #define WX_MNG_SWFW_SYNC_SW_MB … #define WX_MNG_SWFW_SYNC_SW_FLASH … #define WX_MNG_MBOX … #define WX_MNG_MBOX_CTL … #define WX_MNG_MBOX_CTL_SWRDY … #define WX_MNG_MBOX_CTL_FWRDY … #define WX_MNG_BMC2OS_CNT … #define WX_MNG_OS2BMC_CNT … /************************************* ETH MAC *****************************/ #define WX_MAC_TX_CFG … #define WX_MAC_TX_CFG_TE … #define WX_MAC_TX_CFG_SPEED_MASK … #define WX_MAC_TX_CFG_SPEED_10G … #define WX_MAC_TX_CFG_SPEED_1G … #define WX_MAC_RX_CFG … #define WX_MAC_RX_CFG_RE … #define WX_MAC_RX_CFG_JE … #define WX_MAC_PKT_FLT … #define WX_MAC_PKT_FLT_PR … #define WX_MAC_WDG_TIMEOUT … #define WX_MAC_RX_FLOW_CTRL … #define WX_MAC_RX_FLOW_CTRL_RFE … /* MDIO Registers */ #define WX_MSCA … #define WX_MSCA_RA(v) … #define WX_MSCA_PA(v) … #define WX_MSCA_DA(v) … #define WX_MSCC … #define WX_MSCC_CMD(v) … enum WX_MSCA_CMD_value { … }; #define WX_MSCC_SADDR … #define WX_MSCC_BUSY … #define WX_MDIO_CLK(v) … #define WX_MDIO_CLAUSE_SELECT … #define WX_MMC_CONTROL … #define WX_MMC_CONTROL_RSTONRD … /********************************* BAR registers ***************************/ /* Interrupt Registers */ #define WX_BME_CTL … #define WX_PX_MISC_IC … #define WX_PX_MISC_ICS … #define WX_PX_MISC_IEN … #define WX_PX_INTA … #define WX_PX_GPIE … #define WX_PX_GPIE_MODEL … #define WX_PX_IC(_i) … #define WX_PX_IMS(_i) … #define WX_PX_IMC(_i) … #define WX_PX_ISB_ADDR_L … #define WX_PX_ISB_ADDR_H … #define WX_PX_TRANSACTION_PENDING … #define WX_PX_ITRSEL … #define WX_PX_ITR(_i) … #define WX_PX_ITR_CNT_WDIS … #define WX_PX_MISC_IVAR … #define WX_PX_IVAR(_i) … #define WX_PX_IVAR_ALLOC_VAL … #define WX_7K_ITR … #define WX_12K_ITR … #define WX_20K_ITR … #define WX_SP_MAX_EITR … #define WX_EM_MAX_EITR … /* transmit DMA Registers */ #define WX_PX_TR_BAL(_i) … #define WX_PX_TR_BAH(_i) … #define WX_PX_TR_WP(_i) … #define WX_PX_TR_RP(_i) … #define WX_PX_TR_CFG(_i) … /* Transmit Config masks */ #define WX_PX_TR_CFG_ENABLE … #define WX_PX_TR_CFG_TR_SIZE_SHIFT … #define WX_PX_TR_CFG_SWFLSH … #define WX_PX_TR_CFG_WTHRESH_SHIFT … #define WX_PX_TR_CFG_THRE_SHIFT … /* Receive DMA Registers */ #define WX_PX_RR_BAL(_i) … #define WX_PX_RR_BAH(_i) … #define WX_PX_RR_WP(_i) … #define WX_PX_RR_RP(_i) … #define WX_PX_RR_CFG(_i) … #define WX_PX_MPRC(_i) … /* PX_RR_CFG bit definitions */ #define WX_PX_RR_CFG_VLAN … #define WX_PX_RR_CFG_DROP_EN … #define WX_PX_RR_CFG_SPLIT_MODE … #define WX_PX_RR_CFG_RR_THER_SHIFT … #define WX_PX_RR_CFG_RR_HDR_SZ … #define WX_PX_RR_CFG_RR_BUF_SZ … #define WX_PX_RR_CFG_BHDRSIZE_SHIFT … #define WX_PX_RR_CFG_BSIZEPKT_SHIFT … #define WX_PX_RR_CFG_RR_SIZE_SHIFT … #define WX_PX_RR_CFG_RR_EN … /* Number of 80 microseconds we wait for PCI Express master disable */ #define WX_PCI_MASTER_DISABLE_TIMEOUT … /****************** Manageablility Host Interface defines ********************/ #define WX_HI_MAX_BLOCK_BYTE_LENGTH … #define WX_HI_COMMAND_TIMEOUT … #define FW_READ_SHADOW_RAM_CMD … #define FW_READ_SHADOW_RAM_LEN … #define FW_DEFAULT_CHECKSUM … #define FW_NVM_DATA_OFFSET … #define FW_MAX_READ_BUFFER_SIZE … #define FW_RESET_CMD … #define FW_RESET_LEN … #define FW_CEM_HDR_LEN … #define FW_CEM_CMD_RESERVED … #define FW_CEM_MAX_RETRIES … #define FW_CEM_RESP_STATUS_SUCCESS … #define WX_SW_REGION_PTR … #define WX_MAC_STATE_DEFAULT … #define WX_MAC_STATE_MODIFIED … #define WX_MAC_STATE_IN_USE … /* BitTimes (BT) conversion */ #define WX_BT2KB(BT) … #define WX_B2BT(BT) … /* Calculate Delay to respond to PFC */ #define WX_PFC_D … /* Calculate Cable Delay */ #define WX_CABLE_DC … /* Calculate Delay incurred from higher layer */ #define WX_HD … /* Calculate Interface Delay */ #define WX_PHY_D … #define WX_MAC_D … #define WX_XAUI_D … #define WX_ID … /* Calculate PCI Bus delay for low thresholds */ #define WX_PCI_DELAY … /* Calculate delay value in bit times */ #define WX_DV(_max_frame_link, _max_frame_tc) … /* Calculate low threshold delay values */ #define WX_LOW_DV(_max_frame_tc) … /* flow control */ #define WX_DEFAULT_FCPAUSE … #define WX_MAX_RXD … #define WX_MAX_TXD … #define WX_MIN_RXD … #define WX_MIN_TXD … /* Number of Transmit and Receive Descriptors must be a multiple of 128 */ #define WX_REQ_RX_DESCRIPTOR_MULTIPLE … #define WX_REQ_TX_DESCRIPTOR_MULTIPLE … #define WX_MAX_JUMBO_FRAME_SIZE … #define VMDQ_P(p) … /* Supported Rx Buffer Sizes */ #define WX_RXBUFFER_256 … #define WX_RXBUFFER_2K … #define WX_MAX_RXBUFFER … #if MAX_SKB_FRAGS < 8 #define WX_RX_BUFSZ … #else #define WX_RX_BUFSZ … #endif #define WX_RX_BUFFER_WRITE … #define WX_MAX_DATA_PER_TXD … /* Tx Descriptors needed, worst case */ #define TXD_USE_COUNT(S) … #define DESC_NEEDED … #define WX_CFG_PORT_ST … /******************* Receive Descriptor bit definitions **********************/ #define WX_RXD_STAT_DD … #define WX_RXD_STAT_EOP … #define WX_RXD_STAT_VP … #define WX_RXD_STAT_L4CS … #define WX_RXD_STAT_IPCS … #define WX_RXD_STAT_OUTERIPCS … #define WX_RXD_ERR_OUTERIPER … #define WX_RXD_ERR_RXE … #define WX_RXD_ERR_TCPE … #define WX_RXD_ERR_IPE … /* RSS Hash results */ #define WX_RXD_RSSTYPE_MASK … #define WX_RXD_RSSTYPE_IPV4_TCP … #define WX_RXD_RSSTYPE_IPV6_TCP … #define WX_RXD_RSSTYPE_IPV4_SCTP … #define WX_RXD_RSSTYPE_IPV6_SCTP … #define WX_RXD_RSSTYPE_IPV4_UDP … #define WX_RXD_RSSTYPE_IPV6_UDP … #define WX_RSS_L4_TYPES_MASK … /* TUN */ #define WX_PTYPE_TUN_IPV4 … #define WX_PTYPE_TUN_IPV6 … /* PKT for TUN */ #define WX_PTYPE_PKT_IPIP … #define WX_PTYPE_PKT_IG … #define WX_PTYPE_PKT_IGM … #define WX_PTYPE_PKT_IGMV … /* PKT for !TUN */ #define WX_PTYPE_PKT_MAC … #define WX_PTYPE_PKT_IP … /* TYP for PKT=mac */ #define WX_PTYPE_TYP_MAC … /* TYP for PKT=ip */ #define WX_PTYPE_PKT_IPV6 … #define WX_PTYPE_TYP_IPFRAG … #define WX_PTYPE_TYP_IP … #define WX_PTYPE_TYP_UDP … #define WX_PTYPE_TYP_TCP … #define WX_PTYPE_TYP_SCTP … /* Packet type non-ip values */ enum wx_l2_ptypes { … }; #define WX_PTYPE_PKT(_pt) … #define WX_PTYPE_TYPL4(_pt) … #define WX_RXD_PKTTYPE(_rxd) … #define WX_RXD_IPV6EX(_rxd) … /*********************** Transmit Descriptor Config Masks ****************/ #define WX_TXD_STAT_DD … #define WX_TXD_DTYP_DATA … #define WX_TXD_PAYLEN_SHIFT … #define WX_TXD_EOP … #define WX_TXD_IFCS … #define WX_TXD_RS … /*********************** Adv Transmit Descriptor Config Masks ****************/ #define WX_TXD_MAC_TSTAMP … #define WX_TXD_DTYP_CTXT … #define WX_TXD_LINKSEC … #define WX_TXD_VLE … #define WX_TXD_TSE … #define WX_TXD_CC … #define WX_TXD_IPSEC … #define WX_TXD_L4CS … #define WX_TXD_IIPCS … #define WX_TXD_EIPCS … #define WX_TXD_PAYLEN_SHIFT … #define WX_TXD_MACLEN_SHIFT … #define WX_TXD_TAG_TPID_SEL_SHIFT … #define WX_TXD_L4LEN_SHIFT … #define WX_TXD_MSS_SHIFT … #define WX_TXD_OUTER_IPLEN_SHIFT … #define WX_TXD_TUNNEL_LEN_SHIFT … #define WX_TXD_TUNNEL_TYPE_SHIFT … #define WX_TXD_TUNNEL_UDP … #define WX_TXD_TUNNEL_GRE … enum wx_tx_flags { … }; /* VLAN info */ #define WX_TX_FLAGS_VLAN_MASK … #define WX_TX_FLAGS_VLAN_SHIFT … /* wx_dec_ptype.mac: outer mac */ enum wx_dec_ptype_mac { … }; /* wx_dec_ptype.[e]ip: outer&encaped ip */ #define WX_DEC_PTYPE_IP_FRAG … enum wx_dec_ptype_ip { … }; /* wx_dec_ptype.etype: encaped type */ enum wx_dec_ptype_etype { … }; /* wx_dec_ptype.proto: payload proto */ enum wx_dec_ptype_prot { … }; /* wx_dec_ptype.layer: payload layer */ enum wx_dec_ptype_layer { … }; struct wx_dec_ptype { … }; /* macro to make the table lines short */ #define WX_PTT(mac, ip, etype, eip, proto, layer) … /* Host Interface Command Structures */ struct wx_hic_hdr { … }; struct wx_hic_hdr2_req { … }; struct wx_hic_hdr2_rsp { … }; wx_hic_hdr2; /* These need to be dword aligned */ struct wx_hic_read_shadow_ram { … }; struct wx_hic_reset { … }; /* Bus parameters */ struct wx_bus_info { … }; struct wx_thermal_sensor_data { … }; enum wx_mac_type { … }; enum sp_media_type { … }; enum em_mac_type { … }; struct wx_mac_info { … }; enum wx_eeprom_type { … }; struct wx_eeprom_info { … }; struct wx_addr_filter_info { … }; struct wx_mac_addr { … }; enum wx_reset_type { … }; struct wx_cb { … }; #define WX_CB(skb) … /* Transmit Descriptor */ wx_tx_desc; /* Receive Descriptor */ wx_rx_desc; struct wx_tx_context_desc { … }; /* if _flag is in _input, return _result */ #define WX_SET_FLAG(_input, _flag, _result) … #define WX_RX_DESC(R, i) … #define WX_TX_DESC(R, i) … #define WX_TX_CTXTDESC(R, i) … /* wrapper around a pointer to a socket buffer, * so a DMA handle can be stored along with the buffer */ struct wx_tx_buffer { … }; struct wx_rx_buffer { … }; struct wx_queue_stats { … }; struct wx_tx_queue_stats { … }; struct wx_rx_queue_stats { … }; /* iterator for handling rings in ring container */ #define wx_for_each_ring(posm, headm) … struct wx_ring_container { … }; struct wx_ring { … } ____cacheline_internodealigned_in_smp; struct wx_q_vector { … }; struct wx_ring_feature { … }; enum wx_ring_f_enum { … }; enum wx_isb_idx { … }; struct wx_fc_info { … }; /* Statistics counters collected by the MAC */ struct wx_hw_stats { … }; enum wx_state { … }; enum wx_pf_flags { … }; struct wx { … }; #define WX_INTR_ALL … #define WX_INTR_Q(i) … /* register operations */ #define wr32(a, reg, value) … #define rd32(a, reg) … #define rd32a(a, reg, offset) … #define wr32a(a, reg, off, val) … static inline u32 rd32m(struct wx *wx, u32 reg, u32 mask) { … } static inline void wr32m(struct wx *wx, u32 reg, u32 mask, u32 field) { … } static inline u64 rd64(struct wx *wx, u32 reg) { … } /* On some domestic CPU platforms, sometimes IO is not synchronized with * flushing memory, here use readl() to flush PCI read and write. */ #define WX_WRITE_FLUSH(H) … #define wx_err(wx, fmt, arg...) … #define wx_dbg(wx, fmt, arg...) … static inline struct wx *phylink_to_wx(struct phylink_config *config) { … } static inline int wx_set_state_reset(struct wx *wx) { … } #endif /* _WX_TYPE_H_ */
Codebase Browser
linux