/* Synopsys DesignWare Core Enterprise Ethernet (XLGMAC) Driver * * Copyright (c) 2017 Synopsys, Inc. (www.synopsys.com) * * This program is dual-licensed; you may select either version 2 of * the GNU General Public License ("GPL") or BSD license ("BSD"). * * This Synopsys DWC XLGMAC software driver and associated documentation * (hereinafter the "Software") is an unsupported proprietary work of * Synopsys, Inc. unless otherwise expressly agreed to in writing between * Synopsys and you. The Software IS NOT an item of Licensed Software or a * Licensed Product under any End User Software License Agreement or * Agreement for Licensed Products with Synopsys or any supplement thereto. * Synopsys is a registered trademark of Synopsys, Inc. Other names included * in the SOFTWARE may be the trademarks of their respective owners. */ #ifndef __DWC_XLGMAC_REG_H__ #define __DWC_XLGMAC_REG_H__ /* MAC register offsets */ #define MAC_TCR … #define MAC_RCR … #define MAC_PFR … #define MAC_HTR0 … #define MAC_VLANTR … #define MAC_VLANHTR … #define MAC_VLANIR … #define MAC_Q0TFCR … #define MAC_RFCR … #define MAC_RQC0R … #define MAC_RQC1R … #define MAC_RQC2R … #define MAC_RQC3R … #define MAC_ISR … #define MAC_IER … #define MAC_VR … #define MAC_HWF0R … #define MAC_HWF1R … #define MAC_HWF2R … #define MAC_MACA0HR … #define MAC_MACA0LR … #define MAC_MACA1HR … #define MAC_MACA1LR … #define MAC_RSSCR … #define MAC_RSSAR … #define MAC_RSSDR … #define MAC_QTFCR_INC … #define MAC_MACA_INC … #define MAC_HTR_INC … #define MAC_RQC2_INC … #define MAC_RQC2_Q_PER_REG … /* MAC register entry bit positions and sizes */ #define MAC_HWF0R_ADDMACADRSEL_POS … #define MAC_HWF0R_ADDMACADRSEL_LEN … #define MAC_HWF0R_ARPOFFSEL_POS … #define MAC_HWF0R_ARPOFFSEL_LEN … #define MAC_HWF0R_EEESEL_POS … #define MAC_HWF0R_EEESEL_LEN … #define MAC_HWF0R_PHYIFSEL_POS … #define MAC_HWF0R_PHYIFSEL_LEN … #define MAC_HWF0R_MGKSEL_POS … #define MAC_HWF0R_MGKSEL_LEN … #define MAC_HWF0R_MMCSEL_POS … #define MAC_HWF0R_MMCSEL_LEN … #define MAC_HWF0R_RWKSEL_POS … #define MAC_HWF0R_RWKSEL_LEN … #define MAC_HWF0R_RXCOESEL_POS … #define MAC_HWF0R_RXCOESEL_LEN … #define MAC_HWF0R_SAVLANINS_POS … #define MAC_HWF0R_SAVLANINS_LEN … #define MAC_HWF0R_SMASEL_POS … #define MAC_HWF0R_SMASEL_LEN … #define MAC_HWF0R_TSSEL_POS … #define MAC_HWF0R_TSSEL_LEN … #define MAC_HWF0R_TSSTSSEL_POS … #define MAC_HWF0R_TSSTSSEL_LEN … #define MAC_HWF0R_TXCOESEL_POS … #define MAC_HWF0R_TXCOESEL_LEN … #define MAC_HWF0R_VLHASH_POS … #define MAC_HWF0R_VLHASH_LEN … #define MAC_HWF1R_ADDR64_POS … #define MAC_HWF1R_ADDR64_LEN … #define MAC_HWF1R_ADVTHWORD_POS … #define MAC_HWF1R_ADVTHWORD_LEN … #define MAC_HWF1R_DBGMEMA_POS … #define MAC_HWF1R_DBGMEMA_LEN … #define MAC_HWF1R_DCBEN_POS … #define MAC_HWF1R_DCBEN_LEN … #define MAC_HWF1R_HASHTBLSZ_POS … #define MAC_HWF1R_HASHTBLSZ_LEN … #define MAC_HWF1R_L3L4FNUM_POS … #define MAC_HWF1R_L3L4FNUM_LEN … #define MAC_HWF1R_NUMTC_POS … #define MAC_HWF1R_NUMTC_LEN … #define MAC_HWF1R_RSSEN_POS … #define MAC_HWF1R_RSSEN_LEN … #define MAC_HWF1R_RXFIFOSIZE_POS … #define MAC_HWF1R_RXFIFOSIZE_LEN … #define MAC_HWF1R_SPHEN_POS … #define MAC_HWF1R_SPHEN_LEN … #define MAC_HWF1R_TSOEN_POS … #define MAC_HWF1R_TSOEN_LEN … #define MAC_HWF1R_TXFIFOSIZE_POS … #define MAC_HWF1R_TXFIFOSIZE_LEN … #define MAC_HWF2R_AUXSNAPNUM_POS … #define MAC_HWF2R_AUXSNAPNUM_LEN … #define MAC_HWF2R_PPSOUTNUM_POS … #define MAC_HWF2R_PPSOUTNUM_LEN … #define MAC_HWF2R_RXCHCNT_POS … #define MAC_HWF2R_RXCHCNT_LEN … #define MAC_HWF2R_RXQCNT_POS … #define MAC_HWF2R_RXQCNT_LEN … #define MAC_HWF2R_TXCHCNT_POS … #define MAC_HWF2R_TXCHCNT_LEN … #define MAC_HWF2R_TXQCNT_POS … #define MAC_HWF2R_TXQCNT_LEN … #define MAC_IER_TSIE_POS … #define MAC_IER_TSIE_LEN … #define MAC_ISR_MMCRXIS_POS … #define MAC_ISR_MMCRXIS_LEN … #define MAC_ISR_MMCTXIS_POS … #define MAC_ISR_MMCTXIS_LEN … #define MAC_ISR_PMTIS_POS … #define MAC_ISR_PMTIS_LEN … #define MAC_ISR_TSIS_POS … #define MAC_ISR_TSIS_LEN … #define MAC_MACA1HR_AE_POS … #define MAC_MACA1HR_AE_LEN … #define MAC_PFR_HMC_POS … #define MAC_PFR_HMC_LEN … #define MAC_PFR_HPF_POS … #define MAC_PFR_HPF_LEN … #define MAC_PFR_HUC_POS … #define MAC_PFR_HUC_LEN … #define MAC_PFR_PM_POS … #define MAC_PFR_PM_LEN … #define MAC_PFR_PR_POS … #define MAC_PFR_PR_LEN … #define MAC_PFR_VTFE_POS … #define MAC_PFR_VTFE_LEN … #define MAC_Q0TFCR_PT_POS … #define MAC_Q0TFCR_PT_LEN … #define MAC_Q0TFCR_TFE_POS … #define MAC_Q0TFCR_TFE_LEN … #define MAC_RCR_ACS_POS … #define MAC_RCR_ACS_LEN … #define MAC_RCR_CST_POS … #define MAC_RCR_CST_LEN … #define MAC_RCR_DCRCC_POS … #define MAC_RCR_DCRCC_LEN … #define MAC_RCR_HDSMS_POS … #define MAC_RCR_HDSMS_LEN … #define MAC_RCR_IPC_POS … #define MAC_RCR_IPC_LEN … #define MAC_RCR_JE_POS … #define MAC_RCR_JE_LEN … #define MAC_RCR_LM_POS … #define MAC_RCR_LM_LEN … #define MAC_RCR_RE_POS … #define MAC_RCR_RE_LEN … #define MAC_RFCR_PFCE_POS … #define MAC_RFCR_PFCE_LEN … #define MAC_RFCR_RFE_POS … #define MAC_RFCR_RFE_LEN … #define MAC_RFCR_UP_POS … #define MAC_RFCR_UP_LEN … #define MAC_RQC0R_RXQ0EN_POS … #define MAC_RQC0R_RXQ0EN_LEN … #define MAC_RSSAR_ADDRT_POS … #define MAC_RSSAR_ADDRT_LEN … #define MAC_RSSAR_CT_POS … #define MAC_RSSAR_CT_LEN … #define MAC_RSSAR_OB_POS … #define MAC_RSSAR_OB_LEN … #define MAC_RSSAR_RSSIA_POS … #define MAC_RSSAR_RSSIA_LEN … #define MAC_RSSCR_IP2TE_POS … #define MAC_RSSCR_IP2TE_LEN … #define MAC_RSSCR_RSSE_POS … #define MAC_RSSCR_RSSE_LEN … #define MAC_RSSCR_TCP4TE_POS … #define MAC_RSSCR_TCP4TE_LEN … #define MAC_RSSCR_UDP4TE_POS … #define MAC_RSSCR_UDP4TE_LEN … #define MAC_RSSDR_DMCH_POS … #define MAC_RSSDR_DMCH_LEN … #define MAC_TCR_SS_POS … #define MAC_TCR_SS_LEN … #define MAC_TCR_TE_POS … #define MAC_TCR_TE_LEN … #define MAC_VLANHTR_VLHT_POS … #define MAC_VLANHTR_VLHT_LEN … #define MAC_VLANIR_VLTI_POS … #define MAC_VLANIR_VLTI_LEN … #define MAC_VLANIR_CSVL_POS … #define MAC_VLANIR_CSVL_LEN … #define MAC_VLANTR_DOVLTC_POS … #define MAC_VLANTR_DOVLTC_LEN … #define MAC_VLANTR_ERSVLM_POS … #define MAC_VLANTR_ERSVLM_LEN … #define MAC_VLANTR_ESVL_POS … #define MAC_VLANTR_ESVL_LEN … #define MAC_VLANTR_ETV_POS … #define MAC_VLANTR_ETV_LEN … #define MAC_VLANTR_EVLS_POS … #define MAC_VLANTR_EVLS_LEN … #define MAC_VLANTR_EVLRXS_POS … #define MAC_VLANTR_EVLRXS_LEN … #define MAC_VLANTR_VL_POS … #define MAC_VLANTR_VL_LEN … #define MAC_VLANTR_VTHM_POS … #define MAC_VLANTR_VTHM_LEN … #define MAC_VLANTR_VTIM_POS … #define MAC_VLANTR_VTIM_LEN … #define MAC_VR_DEVID_POS … #define MAC_VR_DEVID_LEN … #define MAC_VR_SNPSVER_POS … #define MAC_VR_SNPSVER_LEN … #define MAC_VR_USERVER_POS … #define MAC_VR_USERVER_LEN … /* MMC register offsets */ #define MMC_CR … #define MMC_RISR … #define MMC_TISR … #define MMC_RIER … #define MMC_TIER … #define MMC_TXOCTETCOUNT_GB_LO … #define MMC_TXFRAMECOUNT_GB_LO … #define MMC_TXBROADCASTFRAMES_G_LO … #define MMC_TXMULTICASTFRAMES_G_LO … #define MMC_TX64OCTETS_GB_LO … #define MMC_TX65TO127OCTETS_GB_LO … #define MMC_TX128TO255OCTETS_GB_LO … #define MMC_TX256TO511OCTETS_GB_LO … #define MMC_TX512TO1023OCTETS_GB_LO … #define MMC_TX1024TOMAXOCTETS_GB_LO … #define MMC_TXUNICASTFRAMES_GB_LO … #define MMC_TXMULTICASTFRAMES_GB_LO … #define MMC_TXBROADCASTFRAMES_GB_LO … #define MMC_TXUNDERFLOWERROR_LO … #define MMC_TXOCTETCOUNT_G_LO … #define MMC_TXFRAMECOUNT_G_LO … #define MMC_TXPAUSEFRAMES_LO … #define MMC_TXVLANFRAMES_G_LO … #define MMC_RXFRAMECOUNT_GB_LO … #define MMC_RXOCTETCOUNT_GB_LO … #define MMC_RXOCTETCOUNT_G_LO … #define MMC_RXBROADCASTFRAMES_G_LO … #define MMC_RXMULTICASTFRAMES_G_LO … #define MMC_RXCRCERROR_LO … #define MMC_RXRUNTERROR … #define MMC_RXJABBERERROR … #define MMC_RXUNDERSIZE_G … #define MMC_RXOVERSIZE_G … #define MMC_RX64OCTETS_GB_LO … #define MMC_RX65TO127OCTETS_GB_LO … #define MMC_RX128TO255OCTETS_GB_LO … #define MMC_RX256TO511OCTETS_GB_LO … #define MMC_RX512TO1023OCTETS_GB_LO … #define MMC_RX1024TOMAXOCTETS_GB_LO … #define MMC_RXUNICASTFRAMES_G_LO … #define MMC_RXLENGTHERROR_LO … #define MMC_RXOUTOFRANGETYPE_LO … #define MMC_RXPAUSEFRAMES_LO … #define MMC_RXFIFOOVERFLOW_LO … #define MMC_RXVLANFRAMES_GB_LO … #define MMC_RXWATCHDOGERROR … /* MMC register entry bit positions and sizes */ #define MMC_CR_CR_POS … #define MMC_CR_CR_LEN … #define MMC_CR_CSR_POS … #define MMC_CR_CSR_LEN … #define MMC_CR_ROR_POS … #define MMC_CR_ROR_LEN … #define MMC_CR_MCF_POS … #define MMC_CR_MCF_LEN … #define MMC_CR_MCT_POS … #define MMC_CR_MCT_LEN … #define MMC_RIER_ALL_INTERRUPTS_POS … #define MMC_RIER_ALL_INTERRUPTS_LEN … #define MMC_RISR_RXFRAMECOUNT_GB_POS … #define MMC_RISR_RXFRAMECOUNT_GB_LEN … #define MMC_RISR_RXOCTETCOUNT_GB_POS … #define MMC_RISR_RXOCTETCOUNT_GB_LEN … #define MMC_RISR_RXOCTETCOUNT_G_POS … #define MMC_RISR_RXOCTETCOUNT_G_LEN … #define MMC_RISR_RXBROADCASTFRAMES_G_POS … #define MMC_RISR_RXBROADCASTFRAMES_G_LEN … #define MMC_RISR_RXMULTICASTFRAMES_G_POS … #define MMC_RISR_RXMULTICASTFRAMES_G_LEN … #define MMC_RISR_RXCRCERROR_POS … #define MMC_RISR_RXCRCERROR_LEN … #define MMC_RISR_RXRUNTERROR_POS … #define MMC_RISR_RXRUNTERROR_LEN … #define MMC_RISR_RXJABBERERROR_POS … #define MMC_RISR_RXJABBERERROR_LEN … #define MMC_RISR_RXUNDERSIZE_G_POS … #define MMC_RISR_RXUNDERSIZE_G_LEN … #define MMC_RISR_RXOVERSIZE_G_POS … #define MMC_RISR_RXOVERSIZE_G_LEN … #define MMC_RISR_RX64OCTETS_GB_POS … #define MMC_RISR_RX64OCTETS_GB_LEN … #define MMC_RISR_RX65TO127OCTETS_GB_POS … #define MMC_RISR_RX65TO127OCTETS_GB_LEN … #define MMC_RISR_RX128TO255OCTETS_GB_POS … #define MMC_RISR_RX128TO255OCTETS_GB_LEN … #define MMC_RISR_RX256TO511OCTETS_GB_POS … #define MMC_RISR_RX256TO511OCTETS_GB_LEN … #define MMC_RISR_RX512TO1023OCTETS_GB_POS … #define MMC_RISR_RX512TO1023OCTETS_GB_LEN … #define MMC_RISR_RX1024TOMAXOCTETS_GB_POS … #define MMC_RISR_RX1024TOMAXOCTETS_GB_LEN … #define MMC_RISR_RXUNICASTFRAMES_G_POS … #define MMC_RISR_RXUNICASTFRAMES_G_LEN … #define MMC_RISR_RXLENGTHERROR_POS … #define MMC_RISR_RXLENGTHERROR_LEN … #define MMC_RISR_RXOUTOFRANGETYPE_POS … #define MMC_RISR_RXOUTOFRANGETYPE_LEN … #define MMC_RISR_RXPAUSEFRAMES_POS … #define MMC_RISR_RXPAUSEFRAMES_LEN … #define MMC_RISR_RXFIFOOVERFLOW_POS … #define MMC_RISR_RXFIFOOVERFLOW_LEN … #define MMC_RISR_RXVLANFRAMES_GB_POS … #define MMC_RISR_RXVLANFRAMES_GB_LEN … #define MMC_RISR_RXWATCHDOGERROR_POS … #define MMC_RISR_RXWATCHDOGERROR_LEN … #define MMC_TIER_ALL_INTERRUPTS_POS … #define MMC_TIER_ALL_INTERRUPTS_LEN … #define MMC_TISR_TXOCTETCOUNT_GB_POS … #define MMC_TISR_TXOCTETCOUNT_GB_LEN … #define MMC_TISR_TXFRAMECOUNT_GB_POS … #define MMC_TISR_TXFRAMECOUNT_GB_LEN … #define MMC_TISR_TXBROADCASTFRAMES_G_POS … #define MMC_TISR_TXBROADCASTFRAMES_G_LEN … #define MMC_TISR_TXMULTICASTFRAMES_G_POS … #define MMC_TISR_TXMULTICASTFRAMES_G_LEN … #define MMC_TISR_TX64OCTETS_GB_POS … #define MMC_TISR_TX64OCTETS_GB_LEN … #define MMC_TISR_TX65TO127OCTETS_GB_POS … #define MMC_TISR_TX65TO127OCTETS_GB_LEN … #define MMC_TISR_TX128TO255OCTETS_GB_POS … #define MMC_TISR_TX128TO255OCTETS_GB_LEN … #define MMC_TISR_TX256TO511OCTETS_GB_POS … #define MMC_TISR_TX256TO511OCTETS_GB_LEN … #define MMC_TISR_TX512TO1023OCTETS_GB_POS … #define MMC_TISR_TX512TO1023OCTETS_GB_LEN … #define MMC_TISR_TX1024TOMAXOCTETS_GB_POS … #define MMC_TISR_TX1024TOMAXOCTETS_GB_LEN … #define MMC_TISR_TXUNICASTFRAMES_GB_POS … #define MMC_TISR_TXUNICASTFRAMES_GB_LEN … #define MMC_TISR_TXMULTICASTFRAMES_GB_POS … #define MMC_TISR_TXMULTICASTFRAMES_GB_LEN … #define MMC_TISR_TXBROADCASTFRAMES_GB_POS … #define MMC_TISR_TXBROADCASTFRAMES_GB_LEN … #define MMC_TISR_TXUNDERFLOWERROR_POS … #define MMC_TISR_TXUNDERFLOWERROR_LEN … #define MMC_TISR_TXOCTETCOUNT_G_POS … #define MMC_TISR_TXOCTETCOUNT_G_LEN … #define MMC_TISR_TXFRAMECOUNT_G_POS … #define MMC_TISR_TXFRAMECOUNT_G_LEN … #define MMC_TISR_TXPAUSEFRAMES_POS … #define MMC_TISR_TXPAUSEFRAMES_LEN … #define MMC_TISR_TXVLANFRAMES_G_POS … #define MMC_TISR_TXVLANFRAMES_G_LEN … /* MTL register offsets */ #define MTL_OMR … #define MTL_FDDR … #define MTL_RQDCM0R … #define MTL_RQDCM_INC … #define MTL_RQDCM_Q_PER_REG … /* MTL register entry bit positions and sizes */ #define MTL_OMR_ETSALG_POS … #define MTL_OMR_ETSALG_LEN … #define MTL_OMR_RAA_POS … #define MTL_OMR_RAA_LEN … /* MTL queue register offsets * Multiple queues can be active. The first queue has registers * that begin at 0x1100. Each subsequent queue has registers that * are accessed using an offset of 0x80 from the previous queue. */ #define MTL_Q_BASE … #define MTL_Q_INC … #define MTL_Q_TQOMR … #define MTL_Q_RQOMR … #define MTL_Q_RQDR … #define MTL_Q_RQFCR … #define MTL_Q_IER … #define MTL_Q_ISR … /* MTL queue register entry bit positions and sizes */ #define MTL_Q_RQDR_PRXQ_POS … #define MTL_Q_RQDR_PRXQ_LEN … #define MTL_Q_RQDR_RXQSTS_POS … #define MTL_Q_RQDR_RXQSTS_LEN … #define MTL_Q_RQFCR_RFA_POS … #define MTL_Q_RQFCR_RFA_LEN … #define MTL_Q_RQFCR_RFD_POS … #define MTL_Q_RQFCR_RFD_LEN … #define MTL_Q_RQOMR_EHFC_POS … #define MTL_Q_RQOMR_EHFC_LEN … #define MTL_Q_RQOMR_RQS_POS … #define MTL_Q_RQOMR_RQS_LEN … #define MTL_Q_RQOMR_RSF_POS … #define MTL_Q_RQOMR_RSF_LEN … #define MTL_Q_RQOMR_FEP_POS … #define MTL_Q_RQOMR_FEP_LEN … #define MTL_Q_RQOMR_FUP_POS … #define MTL_Q_RQOMR_FUP_LEN … #define MTL_Q_RQOMR_RTC_POS … #define MTL_Q_RQOMR_RTC_LEN … #define MTL_Q_TQOMR_FTQ_POS … #define MTL_Q_TQOMR_FTQ_LEN … #define MTL_Q_TQOMR_Q2TCMAP_POS … #define MTL_Q_TQOMR_Q2TCMAP_LEN … #define MTL_Q_TQOMR_TQS_POS … #define MTL_Q_TQOMR_TQS_LEN … #define MTL_Q_TQOMR_TSF_POS … #define MTL_Q_TQOMR_TSF_LEN … #define MTL_Q_TQOMR_TTC_POS … #define MTL_Q_TQOMR_TTC_LEN … #define MTL_Q_TQOMR_TXQEN_POS … #define MTL_Q_TQOMR_TXQEN_LEN … /* MTL queue register value */ #define MTL_RSF_DISABLE … #define MTL_RSF_ENABLE … #define MTL_TSF_DISABLE … #define MTL_TSF_ENABLE … #define MTL_RX_THRESHOLD_64 … #define MTL_RX_THRESHOLD_96 … #define MTL_RX_THRESHOLD_128 … #define MTL_TX_THRESHOLD_64 … #define MTL_TX_THRESHOLD_96 … #define MTL_TX_THRESHOLD_128 … #define MTL_TX_THRESHOLD_192 … #define MTL_TX_THRESHOLD_256 … #define MTL_TX_THRESHOLD_384 … #define MTL_TX_THRESHOLD_512 … #define MTL_ETSALG_WRR … #define MTL_ETSALG_WFQ … #define MTL_ETSALG_DWRR … #define MTL_RAA_SP … #define MTL_RAA_WSP … #define MTL_Q_DISABLED … #define MTL_Q_ENABLED … #define MTL_RQDCM0R_Q0MDMACH … #define MTL_RQDCM0R_Q1MDMACH … #define MTL_RQDCM0R_Q2MDMACH … #define MTL_RQDCM0R_Q3MDMACH … #define MTL_RQDCM1R_Q4MDMACH … #define MTL_RQDCM1R_Q5MDMACH … #define MTL_RQDCM1R_Q6MDMACH … #define MTL_RQDCM1R_Q7MDMACH … #define MTL_RQDCM2R_Q8MDMACH … #define MTL_RQDCM2R_Q9MDMACH … #define MTL_RQDCM2R_Q10MDMACH … #define MTL_RQDCM2R_Q11MDMACH … /* MTL traffic class register offsets * Multiple traffic classes can be active. The first class has registers * that begin at 0x1100. Each subsequent queue has registers that * are accessed using an offset of 0x80 from the previous queue. */ #define MTL_TC_BASE … #define MTL_TC_INC … #define MTL_TC_ETSCR … #define MTL_TC_ETSSR … #define MTL_TC_QWR … /* MTL traffic class register entry bit positions and sizes */ #define MTL_TC_ETSCR_TSA_POS … #define MTL_TC_ETSCR_TSA_LEN … #define MTL_TC_QWR_QW_POS … #define MTL_TC_QWR_QW_LEN … /* MTL traffic class register value */ #define MTL_TSA_SP … #define MTL_TSA_ETS … /* DMA register offsets */ #define DMA_MR … #define DMA_SBMR … #define DMA_ISR … #define DMA_DSR0 … #define DMA_DSR1 … /* DMA register entry bit positions and sizes */ #define DMA_ISR_MACIS_POS … #define DMA_ISR_MACIS_LEN … #define DMA_ISR_MTLIS_POS … #define DMA_ISR_MTLIS_LEN … #define DMA_MR_SWR_POS … #define DMA_MR_SWR_LEN … #define DMA_SBMR_EAME_POS … #define DMA_SBMR_EAME_LEN … #define DMA_SBMR_BLEN_64_POS … #define DMA_SBMR_BLEN_64_LEN … #define DMA_SBMR_BLEN_128_POS … #define DMA_SBMR_BLEN_128_LEN … #define DMA_SBMR_BLEN_256_POS … #define DMA_SBMR_BLEN_256_LEN … #define DMA_SBMR_UNDEF_POS … #define DMA_SBMR_UNDEF_LEN … /* DMA register values */ #define DMA_DSR_RPS_LEN … #define DMA_DSR_TPS_LEN … #define DMA_DSR_Q_LEN … #define DMA_DSR0_TPS_START … #define DMA_DSRX_FIRST_QUEUE … #define DMA_DSRX_INC … #define DMA_DSRX_QPR … #define DMA_DSRX_TPS_START … #define DMA_TPS_STOPPED … #define DMA_TPS_SUSPENDED … /* DMA channel register offsets * Multiple channels can be active. The first channel has registers * that begin at 0x3100. Each subsequent channel has registers that * are accessed using an offset of 0x80 from the previous channel. */ #define DMA_CH_BASE … #define DMA_CH_INC … #define DMA_CH_CR … #define DMA_CH_TCR … #define DMA_CH_RCR … #define DMA_CH_TDLR_HI … #define DMA_CH_TDLR_LO … #define DMA_CH_RDLR_HI … #define DMA_CH_RDLR_LO … #define DMA_CH_TDTR_LO … #define DMA_CH_RDTR_LO … #define DMA_CH_TDRLR … #define DMA_CH_RDRLR … #define DMA_CH_IER … #define DMA_CH_RIWT … #define DMA_CH_SR … /* DMA channel register entry bit positions and sizes */ #define DMA_CH_CR_PBLX8_POS … #define DMA_CH_CR_PBLX8_LEN … #define DMA_CH_CR_SPH_POS … #define DMA_CH_CR_SPH_LEN … #define DMA_CH_IER_AIE_POS … #define DMA_CH_IER_AIE_LEN … #define DMA_CH_IER_FBEE_POS … #define DMA_CH_IER_FBEE_LEN … #define DMA_CH_IER_NIE_POS … #define DMA_CH_IER_NIE_LEN … #define DMA_CH_IER_RBUE_POS … #define DMA_CH_IER_RBUE_LEN … #define DMA_CH_IER_RIE_POS … #define DMA_CH_IER_RIE_LEN … #define DMA_CH_IER_RSE_POS … #define DMA_CH_IER_RSE_LEN … #define DMA_CH_IER_TBUE_POS … #define DMA_CH_IER_TBUE_LEN … #define DMA_CH_IER_TIE_POS … #define DMA_CH_IER_TIE_LEN … #define DMA_CH_IER_TXSE_POS … #define DMA_CH_IER_TXSE_LEN … #define DMA_CH_RCR_PBL_POS … #define DMA_CH_RCR_PBL_LEN … #define DMA_CH_RCR_RBSZ_POS … #define DMA_CH_RCR_RBSZ_LEN … #define DMA_CH_RCR_SR_POS … #define DMA_CH_RCR_SR_LEN … #define DMA_CH_RIWT_RWT_POS … #define DMA_CH_RIWT_RWT_LEN … #define DMA_CH_SR_FBE_POS … #define DMA_CH_SR_FBE_LEN … #define DMA_CH_SR_RBU_POS … #define DMA_CH_SR_RBU_LEN … #define DMA_CH_SR_RI_POS … #define DMA_CH_SR_RI_LEN … #define DMA_CH_SR_RPS_POS … #define DMA_CH_SR_RPS_LEN … #define DMA_CH_SR_TBU_POS … #define DMA_CH_SR_TBU_LEN … #define DMA_CH_SR_TI_POS … #define DMA_CH_SR_TI_LEN … #define DMA_CH_SR_TPS_POS … #define DMA_CH_SR_TPS_LEN … #define DMA_CH_TCR_OSP_POS … #define DMA_CH_TCR_OSP_LEN … #define DMA_CH_TCR_PBL_POS … #define DMA_CH_TCR_PBL_LEN … #define DMA_CH_TCR_ST_POS … #define DMA_CH_TCR_ST_LEN … #define DMA_CH_TCR_TSE_POS … #define DMA_CH_TCR_TSE_LEN … /* DMA channel register values */ #define DMA_OSP_DISABLE … #define DMA_OSP_ENABLE … #define DMA_PBL_1 … #define DMA_PBL_2 … #define DMA_PBL_4 … #define DMA_PBL_8 … #define DMA_PBL_16 … #define DMA_PBL_32 … #define DMA_PBL_64 … #define DMA_PBL_128 … #define DMA_PBL_256 … #define DMA_PBL_X8_DISABLE … #define DMA_PBL_X8_ENABLE … /* Descriptor/Packet entry bit positions and sizes */ #define RX_PACKET_ERRORS_CRC_POS … #define RX_PACKET_ERRORS_CRC_LEN … #define RX_PACKET_ERRORS_FRAME_POS … #define RX_PACKET_ERRORS_FRAME_LEN … #define RX_PACKET_ERRORS_LENGTH_POS … #define RX_PACKET_ERRORS_LENGTH_LEN … #define RX_PACKET_ERRORS_OVERRUN_POS … #define RX_PACKET_ERRORS_OVERRUN_LEN … #define RX_PACKET_ATTRIBUTES_CSUM_DONE_POS … #define RX_PACKET_ATTRIBUTES_CSUM_DONE_LEN … #define RX_PACKET_ATTRIBUTES_VLAN_CTAG_POS … #define RX_PACKET_ATTRIBUTES_VLAN_CTAG_LEN … #define RX_PACKET_ATTRIBUTES_INCOMPLETE_POS … #define RX_PACKET_ATTRIBUTES_INCOMPLETE_LEN … #define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_POS … #define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_LEN … #define RX_PACKET_ATTRIBUTES_CONTEXT_POS … #define RX_PACKET_ATTRIBUTES_CONTEXT_LEN … #define RX_PACKET_ATTRIBUTES_RX_TSTAMP_POS … #define RX_PACKET_ATTRIBUTES_RX_TSTAMP_LEN … #define RX_PACKET_ATTRIBUTES_RSS_HASH_POS … #define RX_PACKET_ATTRIBUTES_RSS_HASH_LEN … #define RX_NORMAL_DESC0_OVT_POS … #define RX_NORMAL_DESC0_OVT_LEN … #define RX_NORMAL_DESC2_HL_POS … #define RX_NORMAL_DESC2_HL_LEN … #define RX_NORMAL_DESC3_CDA_POS … #define RX_NORMAL_DESC3_CDA_LEN … #define RX_NORMAL_DESC3_CTXT_POS … #define RX_NORMAL_DESC3_CTXT_LEN … #define RX_NORMAL_DESC3_ES_POS … #define RX_NORMAL_DESC3_ES_LEN … #define RX_NORMAL_DESC3_ETLT_POS … #define RX_NORMAL_DESC3_ETLT_LEN … #define RX_NORMAL_DESC3_FD_POS … #define RX_NORMAL_DESC3_FD_LEN … #define RX_NORMAL_DESC3_INTE_POS … #define RX_NORMAL_DESC3_INTE_LEN … #define RX_NORMAL_DESC3_L34T_POS … #define RX_NORMAL_DESC3_L34T_LEN … #define RX_NORMAL_DESC3_LD_POS … #define RX_NORMAL_DESC3_LD_LEN … #define RX_NORMAL_DESC3_OWN_POS … #define RX_NORMAL_DESC3_OWN_LEN … #define RX_NORMAL_DESC3_PL_POS … #define RX_NORMAL_DESC3_PL_LEN … #define RX_NORMAL_DESC3_RSV_POS … #define RX_NORMAL_DESC3_RSV_LEN … #define RX_DESC3_L34T_IPV4_TCP … #define RX_DESC3_L34T_IPV4_UDP … #define RX_DESC3_L34T_IPV4_ICMP … #define RX_DESC3_L34T_IPV6_TCP … #define RX_DESC3_L34T_IPV6_UDP … #define RX_DESC3_L34T_IPV6_ICMP … #define RX_CONTEXT_DESC3_TSA_POS … #define RX_CONTEXT_DESC3_TSA_LEN … #define RX_CONTEXT_DESC3_TSD_POS … #define RX_CONTEXT_DESC3_TSD_LEN … #define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_POS … #define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_LEN … #define TX_PACKET_ATTRIBUTES_TSO_ENABLE_POS … #define TX_PACKET_ATTRIBUTES_TSO_ENABLE_LEN … #define TX_PACKET_ATTRIBUTES_VLAN_CTAG_POS … #define TX_PACKET_ATTRIBUTES_VLAN_CTAG_LEN … #define TX_PACKET_ATTRIBUTES_PTP_POS … #define TX_PACKET_ATTRIBUTES_PTP_LEN … #define TX_CONTEXT_DESC2_MSS_POS … #define TX_CONTEXT_DESC2_MSS_LEN … #define TX_CONTEXT_DESC3_CTXT_POS … #define TX_CONTEXT_DESC3_CTXT_LEN … #define TX_CONTEXT_DESC3_TCMSSV_POS … #define TX_CONTEXT_DESC3_TCMSSV_LEN … #define TX_CONTEXT_DESC3_VLTV_POS … #define TX_CONTEXT_DESC3_VLTV_LEN … #define TX_CONTEXT_DESC3_VT_POS … #define TX_CONTEXT_DESC3_VT_LEN … #define TX_NORMAL_DESC2_HL_B1L_POS … #define TX_NORMAL_DESC2_HL_B1L_LEN … #define TX_NORMAL_DESC2_IC_POS … #define TX_NORMAL_DESC2_IC_LEN … #define TX_NORMAL_DESC2_TTSE_POS … #define TX_NORMAL_DESC2_TTSE_LEN … #define TX_NORMAL_DESC2_VTIR_POS … #define TX_NORMAL_DESC2_VTIR_LEN … #define TX_NORMAL_DESC3_CIC_POS … #define TX_NORMAL_DESC3_CIC_LEN … #define TX_NORMAL_DESC3_CPC_POS … #define TX_NORMAL_DESC3_CPC_LEN … #define TX_NORMAL_DESC3_CTXT_POS … #define TX_NORMAL_DESC3_CTXT_LEN … #define TX_NORMAL_DESC3_FD_POS … #define TX_NORMAL_DESC3_FD_LEN … #define TX_NORMAL_DESC3_FL_POS … #define TX_NORMAL_DESC3_FL_LEN … #define TX_NORMAL_DESC3_LD_POS … #define TX_NORMAL_DESC3_LD_LEN … #define TX_NORMAL_DESC3_OWN_POS … #define TX_NORMAL_DESC3_OWN_LEN … #define TX_NORMAL_DESC3_TCPHDRLEN_POS … #define TX_NORMAL_DESC3_TCPHDRLEN_LEN … #define TX_NORMAL_DESC3_TCPPL_POS … #define TX_NORMAL_DESC3_TCPPL_LEN … #define TX_NORMAL_DESC3_TSE_POS … #define TX_NORMAL_DESC3_TSE_LEN … #define TX_NORMAL_DESC2_VLAN_INSERT … #define XLGMAC_MTL_REG(pdata, n, reg) … #define XLGMAC_DMA_REG(channel, reg) … #endif /* __DWC_XLGMAC_REG_H__ */
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