/* SPDX-License-Identifier: GPL-2.0-only */ /* * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver * * Copyright 2008 JMicron Technology Corporation * https://www.jmicron.com/ * Copyright (c) 2009 - 2010 Guo-Fu Tseng <[email protected]> * * Author: Guo-Fu Tseng <[email protected]> */ #ifndef __JME_H_INCLUDED__ #define __JME_H_INCLUDED__ #include <linux/interrupt.h> #define DRV_NAME … #define DRV_VERSION … #define PCI_DEVICE_ID_JMICRON_JMC250 … #define PCI_DEVICE_ID_JMICRON_JMC260 … /* * Message related definitions */ #define JME_DEF_MSG_ENABLE … #ifdef TX_DEBUG #define tx_dbg … #else #define tx_dbg(priv, fmt, args...) … #endif /* * Extra PCI Configuration space interface */ #define PCI_DCSR_MRRS … #define PCI_DCSR_MRRS_MASK … enum pci_dcsr_mrrs_vals { … }; #define PCI_SPI … enum pci_spi_bits { … }; struct jme_spi_op { … }; enum jme_spi_op_bits { … }; #define HALF_US … #define PCI_PRIV_PE1 … enum pci_priv_pe1_bit_masks { … }; enum pci_priv_pe1_values { … }; /* * Dynamic(adaptive)/Static PCC values */ enum dynamic_pcc_values { … }; struct dynpcc_info { … }; #define PCC_INTERVAL_US … #define PCC_INTERVAL … #define PCC_P3_THRESHOLD … #define PCC_P2_THRESHOLD … #define PCC_INTR_THRESHOLD … #define PCC_TX_TO … #define PCC_TX_CNT … /* * TX/RX Descriptors * * TX/RX Ring DESC Count Must be multiple of 16 and <= 1024 */ #define RING_DESC_ALIGN … #define TX_DESC_SIZE … #define TX_RING_NR … #define TX_RING_ALLOC_SIZE(s) … struct txdesc { … }; enum jme_txdesc_flags_bits { … }; #define TXDESC_MSS_SHIFT … enum jme_txwbdesc_flags_bits { … }; #define RX_DESC_SIZE … #define RX_RING_NR … #define RX_RING_ALLOC_SIZE(s) … #define RX_BUF_DMA_ALIGN … #define RX_PREPAD_SIZE … #define ETH_CRC_LEN … #define RX_VLANHDR_LEN … #define RX_EXTRA_LEN … struct rxdesc { … }; enum jme_rxdesc_flags_bits { … }; enum jme_rxwbdesc_flags_bits { … }; enum jme_rxwbdesc_desccnt_mask { … }; enum jme_rxwbdesc_errstat_bits { … }; /* * Buffer information corresponding to ring descriptors. */ struct jme_buffer_info { … }; /* * The structure holding buffer information and ring descriptors all together. */ struct jme_ring { … }; #define NET_STAT(priv) … #define NETDEV_GET_STATS(netdev, fun_ptr) … #define DECLARE_NET_DEVICE_STATS #define DECLARE_NAPI_STRUCT … #define JME_NAPI_HOLDER(holder) … #define JME_NAPI_WEIGHT(w) … #define JME_NAPI_WEIGHT_VAL(w) … #define JME_NAPI_WEIGHT_SET(w, r) … #define JME_RX_COMPLETE(dev, napis) … #define JME_NAPI_ENABLE(priv) … #define JME_NAPI_DISABLE(priv) … #define JME_RX_SCHEDULE_PREP(priv) … #define JME_RX_SCHEDULE(priv) … /* * Jmac Adapter Private data */ struct jme_adapter { … }; enum jme_flags_bits { … }; #define TX_TIMEOUT … #define JME_REG_LEN … #define MAX_ETHERNET_JUMBO_PACKET_SIZE … static inline struct jme_adapter* jme_napi_priv(struct napi_struct *napi) { … } /* * MMaped I/O Resters */ enum jme_iomap_offsets { … }; enum jme_iomap_lens { … }; enum jme_iomap_regs { … }; /* * TX Control/Status Bits */ enum jme_txcs_bits { … }; enum jme_txcs_value { … }; #define JME_TX_DISABLE_TIMEOUT … /* * TX MAC Control/Status Bits */ enum jme_txmcs_bit_masks { … }; enum jme_txmcs_values { … }; enum jme_txpfc_bits_masks { … }; enum jme_txtrhd_bits_masks { … }; enum jme_txtrhd_shifts { … }; enum jme_txtrhd_values { … }; /* * RX Control/Status Bits */ enum jme_rxcs_bit_masks { … }; enum jme_rxcs_values { … }; #define JME_RX_DISABLE_TIMEOUT … /* * RX MAC Control/Status Bits */ enum jme_rxmcs_bits { … }; /* Extern PHY common register 2 */ #define PHY_GAD_TEST_MODE_1 … #define PHY_GAD_TEST_MODE_MSK … #define JM_PHY_SPEC_REG_READ … #define JM_PHY_SPEC_REG_WRITE … #define PHY_CALIBRATION_DELAY … #define JM_PHY_SPEC_ADDR_REG … #define JM_PHY_SPEC_DATA_REG … #define JM_PHY_EXT_COMM_0_REG … #define JM_PHY_EXT_COMM_1_REG … #define JM_PHY_EXT_COMM_2_REG … #define JM_PHY_EXT_COMM_2_CALI_ENABLE … #define JM_PHY_EXT_COMM_2_CALI_MODE_0 … #define JM_PHY_EXT_COMM_2_CALI_LATCH … #define PCI_PRIV_SHARE_NICCTRL … #define JME_FLAG_PHYEA_ENABLE … /* * Wakeup Frame setup interface registers */ #define WAKEUP_FRAME_NR … #define WAKEUP_FRAME_MASK_DWNR … enum jme_wfoi_bit_masks { … }; enum jme_wfoi_shifts { … }; /* * SMI Related definitions */ enum jme_smi_bit_mask { … }; enum jme_smi_bit_shift { … }; static inline u32 smi_reg_addr(int x) { … } static inline u32 smi_phy_addr(int x) { … } #define JME_PHY_TIMEOUT … #define JME_PHY_REG_NR … /* * Global Host Control */ enum jme_ghc_bit_mask { … }; enum jme_ghc_speed_val { … }; enum jme_ghc_to_clk { … }; enum jme_ghc_txmac_clk { … }; /* * Power management control and status register */ enum jme_pmcs_bit_masks { … }; /* * New PHY Power Control Register */ enum jme_phy_pwr_bit_masks { … }; /* * Giga PHY Status Registers */ enum jme_phy_link_bit_mask { … }; enum jme_phy_link_speed_val { … }; #define JME_SPDRSV_TIMEOUT … /* * SMB Control and Status */ enum jme_smbcsr_bit_mask { … }; enum jme_smbintf_bit_mask { … }; enum jme_smbintf_vals { … }; enum jme_smbintf_shifts { … }; #define JME_EEPROM_RELOAD_TIMEOUT … #define JME_SMB_BUSY_TIMEOUT … #define JME_SMB_LEN … #define JME_EEPROM_MAGIC … /* * Timer Control/Status Register */ enum jme_tmcsr_bit_masks { … }; /* * General Purpose REG-0 */ enum jme_gpreg0_masks { … }; enum jme_gpreg0_vals { … }; /* * General Purpose REG-1 */ enum jme_gpreg1_bit_masks { … }; enum jme_gpreg1_vals { … }; /* * Interrupt Status Bits */ enum jme_interrupt_bits { … }; static const u32 INTR_ENABLE = …; /* * PCC Control Registers */ enum jme_pccrx_masks { … }; enum jme_pcctx_masks { … }; enum jme_pccrx_shifts { … }; enum jme_pcctx_shifts { … }; enum jme_pcctx_bits { … }; /* * Chip Mode Register */ enum jme_chipmode_bit_masks { … }; enum jme_chipmode_shifts { … }; /* * Aggressive Power Mode Control */ enum jme_apmc_bits { … }; enum jme_apmc_values { … }; #define APMC_PHP_SHUTDOWN_DELAY … #ifdef REG_DEBUG static char *MAC_REG_NAME[] = { "JME_TXCS", "JME_TXDBA_LO", "JME_TXDBA_HI", "JME_TXQDC", "JME_TXNDA", "JME_TXMCS", "JME_TXPFC", "JME_TXTRHD", "JME_RXCS", "JME_RXDBA_LO", "JME_RXDBA_HI", "JME_RXQDC", "JME_RXNDA", "JME_RXMCS", "JME_RXUMA_LO", "JME_RXUMA_HI", "JME_RXMCHT_LO", "JME_RXMCHT_HI", "JME_WFODP", "JME_WFOI", "JME_SMI", "JME_GHC", "UNKNOWN", "UNKNOWN", "JME_PMCS"}; static char *PE_REG_NAME[] = { "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "JME_PHY_CS", "UNKNOWN", "JME_PHY_LINK", "UNKNOWN", "UNKNOWN", "UNKNOWN", "JME_SMBCSR", "JME_SMBINTF"}; static char *MISC_REG_NAME[] = { "JME_TMCSR", "JME_GPIO", "JME_GPREG0", "JME_GPREG1", "JME_IEVE", "JME_IREQ", "JME_IENS", "JME_IENC", "JME_PCCRX0", "JME_PCCRX1", "JME_PCCRX2", "JME_PCCRX3", "JME_PCCTX0", "JME_CHIPMODE", "JME_SHBA_HI", "JME_SHBA_LO", "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "JME_TIMER1", "JME_TIMER2", "UNKNOWN", "JME_APMC", "JME_PCCSRX0"}; static inline void reg_dbg(const struct jme_adapter *jme, const char *msg, u32 val, u32 reg) { const char *regname; switch (reg & 0xF00) { case 0x000: regname = MAC_REG_NAME[(reg & 0xFF) >> 2]; break; case 0x400: regname = PE_REG_NAME[(reg & 0xFF) >> 2]; break; case 0x800: regname = MISC_REG_NAME[(reg & 0xFF) >> 2]; break; default: regname = PE_REG_NAME[0]; } printk(KERN_DEBUG "%s: %-20s %08x@%s\n", jme->dev->name, msg, val, regname); } #else static inline void reg_dbg(const struct jme_adapter *jme, const char *msg, u32 val, u32 reg) { … } #endif /* * Read/Write MMaped I/O Registers */ static inline u32 jread32(struct jme_adapter *jme, u32 reg) { … } static inline void jwrite32(struct jme_adapter *jme, u32 reg, u32 val) { … } static inline void jwrite32f(struct jme_adapter *jme, u32 reg, u32 val) { … } /* * PHY Regs */ enum jme_phy_reg17_bit_masks { … }; enum jme_phy_reg17_vals { … }; #define BMSR_ANCOMP … /* * Workaround */ static inline int is_buggy250(unsigned short device, u8 chiprev) { … } static inline int new_phy_power_ctrl(u8 chip_main_rev) { … } /* * Function prototypes */ static int jme_set_link_ksettings(struct net_device *netdev, const struct ethtool_link_ksettings *cmd); static void jme_set_unicastaddr(struct net_device *netdev); static void jme_set_multi(struct net_device *netdev); #endif
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