/* SPDX-License-Identifier: GPL-2.0 */ #ifndef _RRUNNER_H_ #define _RRUNNER_H_ #include <linux/interrupt.h> #if ((BITS_PER_LONG != 32) && (BITS_PER_LONG != 64)) #error "BITS_PER_LONG not defined or not valid" #endif struct rr_regs { … }; /* * Host control register bits. */ #define RR_INT … #define RR_CLEAR_INT … #define NO_SWAP … #define NO_SWAP1 … #define PCI_RESET_NIC … #define HALT_NIC … #define SSTEP_NIC … #define MEM_READ_MULTI … #define NIC_HALTED … #define HALT_INST … #define PARITY_ERR … #define INVALID_INST_B … #define RR_REV_2 … #define RR_REV_MASK … /* * Local control register bits. */ #define INTA_STATE … #define CLEAR_INTA … #define FAST_EEPROM_ACCESS … #define ENABLE_EXTRA_SRAM … #define ENABLE_EXTRA_DESC … #define ENABLE_PARITY … #define FORCE_DMA_PARITY_ERROR … #define ENABLE_EEPROM_WRITE … #define ENABLE_DATA_CACHE … #define SRAM_LO_PARITY_ERR … #define SRAM_HI_PARITY_ERR … /* * PCI state bits. */ #define FORCE_PCI_RESET … #define PROVIDE_LENGTH … #define MASK_DMA_READ_MAX … #define RBURST_DISABLE … #define RBURST_4 … #define RBURST_16 … #define RBURST_32 … #define RBURST_64 … #define RBURST_128 … #define RBURST_256 … #define RBURST_1024 … #define MASK_DMA_WRITE_MAX … #define WBURST_DISABLE … #define WBURST_4 … #define WBURST_16 … #define WBURST_32 … #define WBURST_64 … #define WBURST_128 … #define WBURST_256 … #define WBURST_1024 … #define MASK_MIN_DMA … #define FIFO_RETRY_ENABLE … /* * Event register */ #define DMA_WRITE_DONE … #define DMA_READ_DONE … #define DMA_WRITE_ERR … #define DMA_READ_ERR … /* * Receive state * * RoadRunner HIPPI Receive State Register controls and monitors the * HIPPI receive interface in the NIC. Look at err bits when a HIPPI * receive Error Event occurs. */ #define ENABLE_NEW_CON … #define RESET_RECV … #define RECV_ALL … #define RECV_1K … #define RECV_2K … #define RECV_4K … #define RECV_8K … #define RECV_16K … #define RECV_32K … #define RECV_64K … /* * Transmit status. */ #define ENA_XMIT … #define PERM_CON … /* * DMA write state */ #define RESET_DMA … #define NO_SWAP_DMA … #define DMA_ACTIVE … #define THRESH_MASK … #define DMA_ERROR_MASK … /* * Gooddies stored in the ULA registers. */ #define TRACE_ON_WHAT_BIT … #define ONEM_BUF_WHAT_BIT … #define CHAR_API_WHAT_BIT … #define CMD_EVT_WHAT_BIT … #define LONG_TX_WHAT_BIT … #define LONG_RX_WHAT_BIT … #define WHAT_BIT_MASK … /* * Mode status */ #define EVENT_OVFL … #define FATAL_ERR … #define LOOP_BACK … #define MODE_PH … #define MODE_FP … #define PTR64BIT … #define PTR32BIT … #define PTR_WD_SWAP … #define PTR_WD_NOSWAP … #define POST_WARN_EVENT … #define ERR_TERM … #define DIRECT_CONN … #define NO_NIC_WATCHDOG … #define SWAP_DATA … #define SWAP_CONTROL … #define NIC_HALT_ON_ERR … #define NIC_NO_RESTART … #define HALF_DUP_TX … #define HALF_DUP_RX … /* * Error codes */ /* Host Error Codes - values of fail1 */ #define ERR_UNKNOWN_MBOX … #define ERR_UNKNOWN_CMD … #define ERR_MAX_RING … #define ERR_RING_CLOSED … #define ERR_RING_OPEN … /* Firmware internal errors */ #define ERR_EVENT_RING_FULL … #define ERR_DW_PEND_CMND_FULL … #define ERR_DR_PEND_CMND_FULL … #define ERR_DW_PEND_DATA_FULL … #define ERR_DR_PEND_DATA_FULL … #define ERR_ILLEGAL_JUMP … #define ERR_UNIMPLEMENTED … #define ERR_TX_INFO_FULL … #define ERR_RX_INFO_FULL … #define ERR_ILLEGAL_MODE … #define ERR_MAIN_TIMEOUT … #define ERR_EVENT_BITS … #define ERR_UNPEND_FULL … #define ERR_TIMER_QUEUE_FULL … #define ERR_TIMER_QUEUE_EMPTY … #define ERR_TIMER_NO_FREE … #define ERR_INTR_START … #define ERR_BAD_STARTUP … #define ERR_NO_PKT_END … #define ERR_HALTED_ON_ERR … /* Hardware NIC Errors */ #define ERR_WRITE_DMA … #define ERR_READ_DMA … #define ERR_EXT_SERIAL … #define ERR_TX_INT_PARITY … /* * Event definitions */ #define EVT_RING_ENTRIES … #define EVT_RING_SIZE … struct event { … }; /* * General Events */ #define E_NIC_UP … #define E_WATCHDOG … #define E_STAT_UPD … #define E_INVAL_CMD … #define E_SET_CMD_CONS … #define E_LINK_ON … #define E_LINK_OFF … #define E_INTERN_ERR … #define E_HOST_ERR … #define E_STATS_UPDATE … #define E_REJECTING … /* * Send Events */ #define E_CON_REJ … #define E_CON_TMOUT … #define E_CON_NC_TMOUT … #define E_DISC_ERR … #define E_INT_PRTY … #define E_TX_IDLE … #define E_TX_LINK_DROP … #define E_TX_INV_RNG … #define E_TX_INV_BUF … #define E_TX_INV_DSC … /* * Destination Events */ /* * General Receive events */ #define E_VAL_RNG … #define E_RX_RNG_ENER … #define E_INV_RNG … #define E_RX_RNG_SPC … #define E_RX_RNG_OUT … #define E_PKT_DISCARD … #define E_INFO_EVT … /* * Data corrupted events */ #define E_RX_PAR_ERR … #define E_RX_LLRC_ERR … #define E_IP_CKSM_ERR … #define E_DTA_CKSM_ERR … #define E_SHT_BST … /* * Data lost events */ #define E_LST_LNK_ERR … #define E_FLG_SYN_ERR … #define E_FRM_ERR … #define E_RX_IDLE … #define E_PKT_LN_ERR … #define E_STATE_ERR … #define E_UNEXP_DATA … /* * Fatal events */ #define E_RX_INV_BUF … #define E_RX_INV_DSC … #define E_RNG_BLK … /* * Warning events */ #define E_RX_TO … #define E_BFR_SPC … #define E_INV_ULP … #define E_NOT_IMPLEMENTED … /* * Commands */ #define CMD_RING_ENTRIES … struct cmd { … }; #define C_START_FW … #define C_UPD_STAT … #define C_WATCHDOG … #define C_DEL_RNG … #define C_NEW_RNG … #define C_CONN … /* * Mode bits */ #define PACKET_BAD … #define INTERRUPT … #define TX_IP_CKSUM … #define PACKET_END … #define PACKET_START … #define SAME_IFIELD … rraddr; static inline void set_rraddr(rraddr *ra, dma_addr_t addr) { … } static inline void set_rxaddr(struct rr_regs __iomem *regs, volatile dma_addr_t addr) { … } static inline void set_infoaddr(struct rr_regs __iomem *regs, volatile dma_addr_t addr) { … } /* * TX ring */ #ifdef CONFIG_ROADRUNNER_LARGE_RINGS #define TX_RING_ENTRIES … #else #define TX_RING_ENTRIES … #endif #define TX_TOTAL_SIZE … struct tx_desc{ … }; #ifdef CONFIG_ROADRUNNER_LARGE_RINGS #define RX_RING_ENTRIES … #else #define RX_RING_ENTRIES … #endif #define RX_TOTAL_SIZE … struct rx_desc{ … }; /* * ioctl's */ #define SIOCRRPFW … #define SIOCRRGFW … #define SIOCRRID … struct seg_hdr { … }; #define EEPROM_BASE … #define EEPROM_WORDS … #define EEPROM_BYTES … struct eeprom_boot { … }; struct eeprom_manf { … }; struct eeprom_phase_info { … }; struct eeprom_rncd_info { … }; /* Phase 1 region (starts are word offset 0x80) */ struct phase1_hdr{ … }; struct eeprom { … }; struct rr_stats { … }; /* * This struct is shared with the NIC firmware. */ struct ring_ctrl { … }; struct rr_info { … }; /* * The linux structure for the RoadRunner. * * RX/TX descriptors are put first to make sure they are properly * aligned and do not cross cache-line boundaries. */ struct rr_private { … }; /* * Prototypes */ static int rr_init(struct net_device *dev); static int rr_init1(struct net_device *dev); static irqreturn_t rr_interrupt(int irq, void *dev_id); static int rr_open(struct net_device *dev); static netdev_tx_t rr_start_xmit(struct sk_buff *skb, struct net_device *dev); static int rr_close(struct net_device *dev); static int rr_siocdevprivate(struct net_device *dev, struct ifreq *rq, void __user *data, int cmd); static unsigned int rr_read_eeprom(struct rr_private *rrpriv, unsigned long offset, unsigned char *buf, unsigned long length); static u32 rr_read_eeprom_word(struct rr_private *rrpriv, size_t offset); static int rr_load_firmware(struct net_device *dev); static inline void rr_raz_tx(struct rr_private *, struct net_device *); static inline void rr_raz_rx(struct rr_private *, struct net_device *); #endif /* _RRUNNER_H_ */
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