/* SPDX-License-Identifier: GPL-2.0 */ /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. * Copyright (C) 2018-2024 Linaro Ltd. */ #ifndef _IPA_REG_H_ #define _IPA_REG_H_ #include "reg.h" struct platform_device; struct ipa; /** * DOC: IPA Registers * * IPA registers are located within the "ipa-reg" address space defined by * Device Tree. Each register has a specified offset within that space, * which is mapped into virtual memory space in ipa_mem_init(). Each * has a unique identifer, taken from the ipa_reg_id enumerated type. * All IPA registers are 32 bits wide. * * Certain "parameterized" register types are duplicated for a number of * instances of something. For example, each IPA endpoint has an set of * registers defining its configuration. The offset to an endpoint's set * of registers is computed based on an "base" offset, plus an endpoint's * ID multiplied and a "stride" value for the register. Similarly, some * registers have an offset that depends on execution environment. In * this case, the stride is multiplied by a member of the gsi_ee_id * enumerated type. * * Each version of IPA implements an array of ipa_reg structures indexed * by register ID. Each entry in the array specifies the base offset and * (for parameterized registers) a non-zero stride value. Not all versions * of IPA define all registers. The offset for a register is returned by * reg_offset() when the register's ipa_reg structure is supplied; * zero is returned for an undefined register (this should never happen). * * Some registers encode multiple fields within them. Each field in * such a register has a unique identifier (from an enumerated type). * The position and width of the fields in a register are defined by * an array of field masks, indexed by field ID. Two functions are * used to access register fields; both take an ipa_reg structure as * argument. To encode a value to be represented in a register field, * the value and field ID are passed to reg_encode(). To extract * a value encoded in a register field, the field ID is passed to * reg_decode(). In addition, for single-bit fields, reg_bit() * can be used to either encode the bit value, or to generate a mask * used to extract the bit value. */ /* enum ipa_reg_id - IPA register IDs */ enum ipa_reg_id { … }; /* COMP_CFG register */ enum ipa_reg_comp_cfg_field_id { … }; /* CLKON_CFG register */ enum ipa_reg_clkon_cfg_field_id { … }; /* ROUTE register */ enum ipa_reg_route_field_id { … }; /* SHARED_MEM_SIZE register */ enum ipa_reg_shared_mem_size_field_id { … }; /* QSB_MAX_WRITES register */ enum ipa_reg_qsb_max_writes_field_id { … }; /* QSB_MAX_READS register */ enum ipa_reg_qsb_max_reads_field_id { … }; /* FILT_ROUT_HASH_EN and FILT_ROUT_HASH_FLUSH registers */ enum ipa_reg_filt_rout_hash_field_id { … }; /* FILT_ROUT_CACHE_FLUSH register */ enum ipa_reg_filt_rout_cache_field_id { … }; /* BCR register */ enum ipa_bcr_compat { … }; /* LOCAL_PKT_PROC_CNTXT register */ enum ipa_reg_local_pkt_proc_cntxt_field_id { … }; /* COUNTER_CFG register */ enum ipa_reg_counter_cfg_field_id { … }; /* IPA_TX_CFG register */ enum ipa_reg_ipa_tx_cfg_field_id { … }; /* FLAVOR_0 register */ enum ipa_reg_flavor_0_field_id { … }; /* IDLE_INDICATION_CFG register */ enum ipa_reg_idle_indication_cfg_field_id { … }; /* QTIME_TIMESTAMP_CFG register */ enum ipa_reg_qtime_timestamp_cfg_field_id { … }; /* TIMERS_XO_CLK_DIV_CFG register */ enum ipa_reg_timers_xo_clk_div_cfg_field_id { … }; /* TIMERS_PULSE_GRAN_CFG register */ enum ipa_reg_timers_pulse_gran_cfg_field_id { … }; /* Values for IPA_GRAN_x fields of TIMERS_PULSE_GRAN_CFG */ enum ipa_pulse_gran { … }; /* {SRC,DST}_RSRC_GRP_{01,23,45,67}_RSRC_TYPE registers */ enum ipa_reg_rsrc_grp_rsrc_type_field_id { … }; /* ENDP_INIT_CTRL register */ enum ipa_reg_endp_init_ctrl_field_id { … }; /* ENDP_INIT_CFG register */ enum ipa_reg_endp_init_cfg_field_id { … }; /** enum ipa_cs_offload_en - ENDP_INIT_CFG register CS_OFFLOAD_EN field value */ enum ipa_cs_offload_en { … }; /* ENDP_INIT_NAT register */ enum ipa_reg_endp_init_nat_field_id { … }; /** enum ipa_nat_type - ENDP_INIT_NAT register NAT_EN field value */ enum ipa_nat_type { … }; /* ENDP_INIT_HDR register */ enum ipa_reg_endp_init_hdr_field_id { … }; /* ENDP_INIT_HDR_EXT register */ enum ipa_reg_endp_init_hdr_ext_field_id { … }; /* ENDP_INIT_MODE register */ enum ipa_reg_endp_init_mode_field_id { … }; /** enum ipa_mode - ENDP_INIT_MODE register MODE field value */ enum ipa_mode { … }; /* ENDP_INIT_AGGR register */ enum ipa_reg_endp_init_aggr_field_id { … }; /** enum ipa_aggr_en - ENDP_INIT_AGGR register AGGR_EN field value */ enum ipa_aggr_en { … }; /** enum ipa_aggr_type - ENDP_INIT_AGGR register AGGR_TYPE field value */ enum ipa_aggr_type { … }; /* ENDP_INIT_HOL_BLOCK_EN register */ enum ipa_reg_endp_init_hol_block_en_field_id { … }; /* ENDP_INIT_HOL_BLOCK_TIMER register */ enum ipa_reg_endp_init_hol_block_timer_field_id { … }; /* ENDP_INIT_DEAGGR register */ enum ipa_reg_endp_deaggr_field_id { … }; /* ENDP_INIT_RSRC_GRP register */ enum ipa_reg_endp_init_rsrc_grp_field_id { … }; /* ENDP_INIT_SEQ register */ enum ipa_reg_endp_init_seq_field_id { … }; /** * enum ipa_seq_type - HPS and DPS sequencer type * @IPA_SEQ_DMA: Perform DMA only * @IPA_SEQ_1_PASS: One pass through the pipeline * @IPA_SEQ_2_PASS_SKIP_LAST_UC: Two passes, skip the microcprocessor * @IPA_SEQ_1_PASS_SKIP_LAST_UC: One pass, skip the microcprocessor * @IPA_SEQ_2_PASS: Two passes through the pipeline * @IPA_SEQ_3_PASS_SKIP_LAST_UC: Three passes, skip the microcprocessor * @IPA_SEQ_DECIPHER: Optional deciphering step (combined) * * The low-order byte of the sequencer type register defines the number of * passes a packet takes through the IPA pipeline. The last pass through can * optionally skip the microprocessor. Deciphering is optional for all types; * if enabled, an additional mask (two bits) is added to the type value. * * Note: not all combinations of ipa_seq_type and ipa_seq_rep_type are * supported (or meaningful). */ enum ipa_seq_type { … }; /** * enum ipa_seq_rep_type - replicated packet sequencer type * @IPA_SEQ_REP_DMA_PARSER: DMA parser for replicated packets * * This goes in the second byte of the endpoint sequencer type register. * * Note: not all combinations of ipa_seq_type and ipa_seq_rep_type are * supported (or meaningful). */ enum ipa_seq_rep_type { … }; /* ENDP_STATUS register */ enum ipa_reg_endp_status_field_id { … }; /* ENDP_FILTER_ROUTER_HSH_CFG register */ enum ipa_reg_endp_filter_router_hsh_cfg_field_id { … }; /* ENDP_FILTER_CACHE_CFG and ENDP_ROUTER_CACHE_CFG registers */ enum ipa_reg_endp_cache_cfg_field_id { … }; /* IPA_IRQ_STTS, IPA_IRQ_EN, and IPA_IRQ_CLR registers */ /** * enum ipa_irq_id - Bit positions representing type of IPA IRQ * @IPA_IRQ_UC_0: Microcontroller event interrupt * @IPA_IRQ_UC_1: Microcontroller response interrupt * @IPA_IRQ_TX_SUSPEND: Data ready interrupt * @IPA_IRQ_COUNT: Number of IRQ ids (must be last) * * IRQ types not described above are not currently used. * * @IPA_IRQ_BAD_SNOC_ACCESS: (Not currently used) * @IPA_IRQ_EOT_COAL: (Not currently used) * @IPA_IRQ_UC_2: (Not currently used) * @IPA_IRQ_UC_3: (Not currently used) * @IPA_IRQ_UC_IN_Q_NOT_EMPTY: (Not currently used) * @IPA_IRQ_UC_RX_CMD_Q_NOT_FULL: (Not currently used) * @IPA_IRQ_PROC_UC_ACK_Q_NOT_EMPTY: (Not currently used) * @IPA_IRQ_RX_ERR: (Not currently used) * @IPA_IRQ_DEAGGR_ERR: (Not currently used) * @IPA_IRQ_TX_ERR: (Not currently used) * @IPA_IRQ_STEP_MODE: (Not currently used) * @IPA_IRQ_PROC_ERR: (Not currently used) * @IPA_IRQ_TX_HOLB_DROP: (Not currently used) * @IPA_IRQ_BAM_GSI_IDLE: (Not currently used) * @IPA_IRQ_PIPE_YELLOW_BELOW: (Not currently used) * @IPA_IRQ_PIPE_RED_BELOW: (Not currently used) * @IPA_IRQ_PIPE_YELLOW_ABOVE: (Not currently used) * @IPA_IRQ_PIPE_RED_ABOVE: (Not currently used) * @IPA_IRQ_UCP: (Not currently used) * @IPA_IRQ_DCMP: (Not currently used) * @IPA_IRQ_GSI_EE: (Not currently used) * @IPA_IRQ_GSI_IPA_IF_TLV_RCVD: (Not currently used) * @IPA_IRQ_GSI_UC: (Not currently used) * @IPA_IRQ_TLV_LEN_MIN_DSM: (Not currently used) * @IPA_IRQ_DRBIP_PKT_EXCEED_MAX_SIZE_EN: (Not currently used) * @IPA_IRQ_DRBIP_DATA_SCTR_CFG_ERROR_EN: (Not currently used) * @IPA_IRQ_DRBIP_IMM_CMD_NO_FLSH_HZRD_EN: (Not currently used) * @IPA_IRQ_ERROR_NON_FATAL: (Not currently used) * @IPA_IRQ_ERROR_FATAL: (Not currently used) */ enum ipa_irq_id { … }; /* IPA_IRQ_UC register */ enum ipa_reg_ipa_irq_uc_field_id { … }; extern const struct regs ipa_regs_v3_1; extern const struct regs ipa_regs_v3_5_1; extern const struct regs ipa_regs_v4_2; extern const struct regs ipa_regs_v4_5; extern const struct regs ipa_regs_v4_7; extern const struct regs ipa_regs_v4_9; extern const struct regs ipa_regs_v4_11; extern const struct regs ipa_regs_v5_0; extern const struct regs ipa_regs_v5_5; const struct reg *ipa_reg(struct ipa *ipa, enum ipa_reg_id reg_id); int ipa_reg_init(struct ipa *ipa, struct platform_device *pdev); void ipa_reg_exit(struct ipa *ipa); #endif /* _IPA_REG_H_ */
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