/* SPDX-License-Identifier: GPL-2.0 */ #ifndef B43_H_ #define B43_H_ #include <linux/kernel.h> #include <linux/spinlock.h> #include <linux/interrupt.h> #include <linux/hw_random.h> #include <linux/bcma/bcma.h> #include <linux/ssb/ssb.h> #include <linux/completion.h> #include <net/mac80211.h> #include "debugfs.h" #include "leds.h" #include "rfkill.h" #include "bus.h" #include "lo.h" #include "phy_common.h" #ifdef CONFIG_B43_DEBUG #define B43_DEBUG … #else #define B43_DEBUG … #endif /* MMIO offsets */ #define B43_MMIO_DMA0_REASON … #define B43_MMIO_DMA0_IRQ_MASK … #define B43_MMIO_DMA1_REASON … #define B43_MMIO_DMA1_IRQ_MASK … #define B43_MMIO_DMA2_REASON … #define B43_MMIO_DMA2_IRQ_MASK … #define B43_MMIO_DMA3_REASON … #define B43_MMIO_DMA3_IRQ_MASK … #define B43_MMIO_DMA4_REASON … #define B43_MMIO_DMA4_IRQ_MASK … #define B43_MMIO_DMA5_REASON … #define B43_MMIO_DMA5_IRQ_MASK … #define B43_MMIO_MACCTL … #define B43_MMIO_MACCMD … #define B43_MMIO_GEN_IRQ_REASON … #define B43_MMIO_GEN_IRQ_MASK … #define B43_MMIO_RAM_CONTROL … #define B43_MMIO_RAM_DATA … #define B43_MMIO_PS_STATUS … #define B43_MMIO_RADIO_HWENABLED_HI … #define B43_MMIO_MAC_HW_CAP … #define B43_MMIO_SHM_CONTROL … #define B43_MMIO_SHM_DATA … #define B43_MMIO_SHM_DATA_UNALIGNED … #define B43_MMIO_XMITSTAT_0 … #define B43_MMIO_XMITSTAT_1 … #define B43_MMIO_REV3PLUS_TSF_LOW … #define B43_MMIO_REV3PLUS_TSF_HIGH … #define B43_MMIO_TSF_CFP_REP … #define B43_MMIO_TSF_CFP_START … #define B43_MMIO_TSF_CFP_MAXDUR … /* 32-bit DMA */ #define B43_MMIO_DMA32_BASE0 … #define B43_MMIO_DMA32_BASE1 … #define B43_MMIO_DMA32_BASE2 … #define B43_MMIO_DMA32_BASE3 … #define B43_MMIO_DMA32_BASE4 … #define B43_MMIO_DMA32_BASE5 … /* 64-bit DMA */ #define B43_MMIO_DMA64_BASE0 … #define B43_MMIO_DMA64_BASE1 … #define B43_MMIO_DMA64_BASE2 … #define B43_MMIO_DMA64_BASE3 … #define B43_MMIO_DMA64_BASE4 … #define B43_MMIO_DMA64_BASE5 … /* PIO on core rev < 11 */ #define B43_MMIO_PIO_BASE0 … #define B43_MMIO_PIO_BASE1 … #define B43_MMIO_PIO_BASE2 … #define B43_MMIO_PIO_BASE3 … #define B43_MMIO_PIO_BASE4 … #define B43_MMIO_PIO_BASE5 … #define B43_MMIO_PIO_BASE6 … #define B43_MMIO_PIO_BASE7 … /* PIO on core rev >= 11 */ #define B43_MMIO_PIO11_BASE0 … #define B43_MMIO_PIO11_BASE1 … #define B43_MMIO_PIO11_BASE2 … #define B43_MMIO_PIO11_BASE3 … #define B43_MMIO_PIO11_BASE4 … #define B43_MMIO_PIO11_BASE5 … #define B43_MMIO_RADIO24_CONTROL … #define B43_MMIO_RADIO24_DATA … #define B43_MMIO_PHY_VER … #define B43_MMIO_PHY_RADIO … #define B43_MMIO_PHY0 … #define B43_MMIO_ANTENNA … #define B43_MMIO_CHANNEL … #define B43_MMIO_CHANNEL_EXT … #define B43_MMIO_RADIO_CONTROL … #define B43_MMIO_RADIO_DATA_HIGH … #define B43_MMIO_RADIO_DATA_LOW … #define B43_MMIO_PHY_CONTROL … #define B43_MMIO_PHY_DATA … #define B43_MMIO_MACFILTER_CONTROL … #define B43_MMIO_MACFILTER_DATA … #define B43_MMIO_RCMTA_COUNT … #define B43_MMIO_PSM_PHY_HDR … #define B43_MMIO_RADIO_HWENABLED_LO … #define B43_MMIO_GPIO_CONTROL … #define B43_MMIO_GPIO_MASK … #define B43_MMIO_TXE0_CTL … #define B43_MMIO_TXE0_AUX … #define B43_MMIO_TXE0_TS_LOC … #define B43_MMIO_TXE0_TIME_OUT … #define B43_MMIO_TXE0_WM_0 … #define B43_MMIO_TXE0_WM_1 … #define B43_MMIO_TXE0_PHYCTL … #define B43_MMIO_TXE0_STATUS … #define B43_MMIO_TXE0_MMPLCP0 … #define B43_MMIO_TXE0_MMPLCP1 … #define B43_MMIO_TXE0_PHYCTL1 … #define B43_MMIO_XMTFIFODEF … #define B43_MMIO_XMTFIFO_FRAME_CNT … #define B43_MMIO_XMTFIFO_BYTE_CNT … #define B43_MMIO_XMTFIFO_HEAD … #define B43_MMIO_XMTFIFO_RD_PTR … #define B43_MMIO_XMTFIFO_WR_PTR … #define B43_MMIO_XMTFIFODEF1 … #define B43_MMIO_XMTFIFOCMD … #define B43_MMIO_XMTFIFOFLUSH … #define B43_MMIO_XMTFIFOTHRESH … #define B43_MMIO_XMTFIFORDY … #define B43_MMIO_XMTFIFOPRIRDY … #define B43_MMIO_XMTFIFORQPRI … #define B43_MMIO_XMTTPLATETXPTR … #define B43_MMIO_XMTTPLATEPTR … #define B43_MMIO_SMPL_CLCT_STRPTR … #define B43_MMIO_SMPL_CLCT_STPPTR … #define B43_MMIO_SMPL_CLCT_CURPTR … #define B43_MMIO_XMTTPLATEDATALO … #define B43_MMIO_XMTTPLATEDATAHI … #define B43_MMIO_XMTSEL … #define B43_MMIO_XMTTXCNT … #define B43_MMIO_XMTTXSHMADDR … #define B43_MMIO_TSF_CFP_START_LOW … #define B43_MMIO_TSF_CFP_START_HIGH … #define B43_MMIO_TSF_CFP_PRETBTT … #define B43_MMIO_TSF_CLK_FRAC_LOW … #define B43_MMIO_TSF_CLK_FRAC_HIGH … #define B43_MMIO_TSF_0 … #define B43_MMIO_TSF_1 … #define B43_MMIO_TSF_2 … #define B43_MMIO_TSF_3 … #define B43_MMIO_RNG … #define B43_MMIO_IFSSLOT … #define B43_MMIO_IFSCTL … #define B43_MMIO_IFSSTAT … #define B43_MMIO_IFSMEDBUSYCTL … #define B43_MMIO_IFTXDUR … #define B43_MMIO_IFSCTL_USE_EDCF … #define B43_MMIO_POWERUP_DELAY … #define B43_MMIO_BTCOEX_CTL … #define B43_MMIO_BTCOEX_STAT … #define B43_MMIO_BTCOEX_TXCTL … #define B43_MMIO_WEPCTL … /* SPROM boardflags_lo values */ #define B43_BFL_BTCOEXIST … #define B43_BFL_PACTRL … #define B43_BFL_AIRLINEMODE … #define B43_BFL_RSSI … #define B43_BFL_ENETSPI … #define B43_BFL_XTAL_NOSLOW … #define B43_BFL_CCKHIPWR … #define B43_BFL_ENETADM … #define B43_BFL_ENETVLAN … #define B43_BFL_AFTERBURNER … #define B43_BFL_NOPCI … #define B43_BFL_FEM … #define B43_BFL_EXTLNA … #define B43_BFL_HGPA … #define B43_BFL_BTCMOD … #define B43_BFL_ALTIQ … /* SPROM boardflags_hi values */ #define B43_BFH_NOPA … #define B43_BFH_RSSIINV … #define B43_BFH_PAREF … #define B43_BFH_3TSWITCH … #define B43_BFH_PHASESHIFT … #define B43_BFH_BUCKBOOST … #define B43_BFH_FEM_BT … #define B43_BFH_NOCBUCK … #define B43_BFH_PALDO … #define B43_BFH_EXTLNA_5GHZ … /* SPROM boardflags2_lo values */ #define B43_BFL2_RXBB_INT_REG_DIS … #define B43_BFL2_APLL_WAR … #define B43_BFL2_TXPWRCTRL_EN … #define B43_BFL2_2X4_DIV … #define B43_BFL2_5G_PWRGAIN … #define B43_BFL2_PCIEWAR_OVR … #define B43_BFL2_CAESERS_BRD … #define B43_BFL2_BTC3WIRE … #define B43_BFL2_SKWRKFEM_BRD … #define B43_BFL2_SPUR_WAR … #define B43_BFL2_GPLL_WAR … #define B43_BFL2_SINGLEANT_CCK … #define B43_BFL2_2G_SPUR_WAR … /* SPROM boardflags2_hi values */ #define B43_BFH2_GPLL_WAR2 … #define B43_BFH2_IPALVLSHIFT_3P3 … #define B43_BFH2_INTERNDET_TXIQCAL … #define B43_BFH2_XTALBUFOUTEN … /* GPIO register offset, in both ChipCommon and PCI core. */ #define B43_GPIO_CONTROL … /* SHM Routing */ enum { … }; /* SHM Routing modifiers */ #define B43_SHM_AUTOINC_R … #define B43_SHM_AUTOINC_W … #define B43_SHM_AUTOINC_RW … /* Misc SHM_SHARED offsets */ #define B43_SHM_SH_WLCOREREV … #define B43_SHM_SH_PCTLWDPOS … #define B43_SHM_SH_RXPADOFF … #define B43_SHM_SH_FWCAPA … #define B43_SHM_SH_PHYVER … #define B43_SHM_SH_PHYTYPE … #define B43_SHM_SH_ANTSWAP … #define B43_SHM_SH_HOSTF1 … #define B43_SHM_SH_HOSTF2 … #define B43_SHM_SH_HOSTF3 … #define B43_SHM_SH_RFATT … #define B43_SHM_SH_RADAR … #define B43_SHM_SH_PHYTXNOI … #define B43_SHM_SH_RFRXSP1 … #define B43_SHM_SH_HOSTF4 … #define B43_SHM_SH_CHAN … #define B43_SHM_SH_CHAN_5GHZ … #define B43_SHM_SH_CHAN_40MHZ … #define B43_SHM_SH_MACHW_L … #define B43_SHM_SH_MACHW_H … #define B43_SHM_SH_HOSTF5 … #define B43_SHM_SH_BCMCFIFOID … /* TSSI information */ #define B43_SHM_SH_TSSI_CCK … #define B43_SHM_SH_TSSI_OFDM_A … #define B43_SHM_SH_TSSI_OFDM_G … #define B43_TSSI_MAX … /* SHM_SHARED TX FIFO variables */ #define B43_SHM_SH_SIZE01 … #define B43_SHM_SH_SIZE23 … #define B43_SHM_SH_SIZE45 … #define B43_SHM_SH_SIZE67 … /* SHM_SHARED background noise */ #define B43_SHM_SH_JSSI0 … #define B43_SHM_SH_JSSI1 … #define B43_SHM_SH_JSSIAUX … /* SHM_SHARED crypto engine */ #define B43_SHM_SH_DEFAULTIV … #define B43_SHM_SH_NRRXTRANS … #define B43_SHM_SH_KTP … #define B43_SHM_SH_TKIPTSCTTAK … #define B43_SHM_SH_KEYIDXBLOCK … #define B43_SHM_SH_PSM … /* SHM_SHARED WME variables */ #define B43_SHM_SH_EDCFSTAT … #define B43_SHM_SH_TXFCUR … #define B43_SHM_SH_EDCFQ … /* SHM_SHARED powersave mode related */ #define B43_SHM_SH_SLOTT … #define B43_SHM_SH_DTIMPER … #define B43_SHM_SH_NOSLPZNATDTIM … /* SHM_SHARED beacon/AP variables */ #define B43_SHM_SH_BT_BASE0 … #define B43_SHM_SH_BTL0 … #define B43_SHM_SH_BT_BASE1 … #define B43_SHM_SH_BTL1 … #define B43_SHM_SH_BTSFOFF … #define B43_SHM_SH_TIMBPOS … #define B43_SHM_SH_DTIMP … #define B43_SHM_SH_MCASTCOOKIE … #define B43_SHM_SH_SFFBLIM … #define B43_SHM_SH_LFFBLIM … #define B43_SHM_SH_BEACPHYCTL … #define B43_SHM_SH_EXTNPHYCTL … #define B43_SHM_SH_BCN_LI … /* SHM_SHARED ACK/CTS control */ #define B43_SHM_SH_ACKCTSPHYCTL … /* SHM_SHARED probe response variables */ #define B43_SHM_SH_PRSSID … #define B43_SHM_SH_PRSSIDLEN … #define B43_SHM_SH_PRTLEN … #define B43_SHM_SH_PRMAXTIME … #define B43_SHM_SH_PRPHYCTL … /* SHM_SHARED rate tables */ #define B43_SHM_SH_OFDMDIRECT … #define B43_SHM_SH_OFDMBASIC … #define B43_SHM_SH_CCKDIRECT … #define B43_SHM_SH_CCKBASIC … /* SHM_SHARED microcode soft registers */ #define B43_SHM_SH_UCODEREV … #define B43_SHM_SH_UCODEPATCH … #define B43_SHM_SH_UCODEDATE … #define B43_SHM_SH_UCODETIME … #define B43_SHM_SH_UCODESTAT … #define B43_SHM_SH_UCODESTAT_INVALID … #define B43_SHM_SH_UCODESTAT_INIT … #define B43_SHM_SH_UCODESTAT_ACTIVE … #define B43_SHM_SH_UCODESTAT_SUSP … #define B43_SHM_SH_UCODESTAT_SLEEP … #define B43_SHM_SH_MAXBFRAMES … #define B43_SHM_SH_SPUWKUP … #define B43_SHM_SH_PRETBTT … /* SHM_SHARED tx iq workarounds */ #define B43_SHM_SH_NPHY_TXIQW0 … #define B43_SHM_SH_NPHY_TXIQW1 … #define B43_SHM_SH_NPHY_TXIQW2 … #define B43_SHM_SH_NPHY_TXIQW3 … /* SHM_SHARED tx pwr ctrl */ #define B43_SHM_SH_NPHY_TXPWR_INDX0 … #define B43_SHM_SH_NPHY_TXPWR_INDX1 … /* SHM_SCRATCH offsets */ #define B43_SHM_SC_MINCONT … #define B43_SHM_SC_MAXCONT … #define B43_SHM_SC_CURCONT … #define B43_SHM_SC_SRLIMIT … #define B43_SHM_SC_LRLIMIT … #define B43_SHM_SC_DTIMC … #define B43_SHM_SC_BTL0LEN … #define B43_SHM_SC_BTL1LEN … #define B43_SHM_SC_SCFB … #define B43_SHM_SC_LCFB … /* Hardware Radio Enable masks */ #define B43_MMIO_RADIO_HWENABLED_HI_MASK … #define B43_MMIO_RADIO_HWENABLED_LO_MASK … /* HostFlags. See b43_hf_read/write() */ #define B43_HF_ANTDIVHELP … #define B43_HF_SYMW … #define B43_HF_RXPULLW … #define B43_HF_CCKBOOST … #define B43_HF_BTCOEX … #define B43_HF_GDCW … #define B43_HF_OFDMPABOOST … #define B43_HF_ACPR … #define B43_HF_EDCF … #define B43_HF_TSSIRPSMW … #define B43_HF_20IN40IQW … #define B43_HF_DSCRQ … #define B43_HF_ACIW … #define B43_HF_2060W … #define B43_HF_RADARW … #define B43_HF_USEDEFKEYS … #define B43_HF_AFTERBURNER … #define B43_HF_BT4PRIOCOEX … #define B43_HF_FWKUP … #define B43_HF_VCORECALC … #define B43_HF_PCISCW … #define B43_HF_4318TSSI … #define B43_HF_FBCMCFIFO … #define B43_HF_HWPCTL … #define B43_HF_BTCOEXALT … #define B43_HF_TXBTCHECK … #define B43_HF_SKCFPUP … #define B43_HF_N40W … #define B43_HF_ANTSEL … #define B43_HF_BT3COEXT … #define B43_HF_BTCANT … #define B43_HF_ANTSELEN … #define B43_HF_ANTSELMODE … #define B43_HF_MLADVW … #define B43_HF_PR45960W … /* Firmware capabilities field in SHM (Opensource firmware only) */ #define B43_FWCAPA_HWCRYPTO … #define B43_FWCAPA_QOS … /* MacFilter offsets. */ #define B43_MACFILTER_SELF … #define B43_MACFILTER_BSSID … /* PowerControl */ #define B43_PCTL_IN … #define B43_PCTL_OUT … #define B43_PCTL_OUTENABLE … #define B43_PCTL_XTAL_POWERUP … #define B43_PCTL_PLL_POWERDOWN … /* PowerControl Clock Modes */ #define B43_PCTL_CLK_FAST … #define B43_PCTL_CLK_SLOW … #define B43_PCTL_CLK_DYNAMIC … #define B43_PCTL_FORCE_SLOW … #define B43_PCTL_FORCE_PLL … #define B43_PCTL_DYN_XTAL … /* PHYVersioning */ #define B43_PHYTYPE_A … #define B43_PHYTYPE_B … #define B43_PHYTYPE_G … #define B43_PHYTYPE_N … #define B43_PHYTYPE_LP … #define B43_PHYTYPE_SSLPN … #define B43_PHYTYPE_HT … #define B43_PHYTYPE_LCN … #define B43_PHYTYPE_LCNXN … #define B43_PHYTYPE_LCN40 … #define B43_PHYTYPE_AC … /* PHYRegisters */ #define B43_PHY_ILT_A_CTRL … #define B43_PHY_ILT_A_DATA1 … #define B43_PHY_ILT_A_DATA2 … #define B43_PHY_G_LO_CONTROL … #define B43_PHY_ILT_G_CTRL … #define B43_PHY_ILT_G_DATA1 … #define B43_PHY_ILT_G_DATA2 … #define B43_PHY_A_PCTL … #define B43_PHY_G_PCTL … #define B43_PHY_A_CRS … #define B43_PHY_RADIO_BITFIELD … #define B43_PHY_G_CRS … #define B43_PHY_NRSSILT_CTRL … #define B43_PHY_NRSSILT_DATA … /* RadioRegisters */ #define B43_RADIOCTL_ID … /* MAC Control bitfield */ #define B43_MACCTL_ENABLED … #define B43_MACCTL_PSM_RUN … #define B43_MACCTL_PSM_JMP0 … #define B43_MACCTL_SHM_ENABLED … #define B43_MACCTL_SHM_UPPER … #define B43_MACCTL_IHR_ENABLED … #define B43_MACCTL_PSM_DBG … #define B43_MACCTL_GPOUTSMSK … #define B43_MACCTL_BE … #define B43_MACCTL_INFRA … #define B43_MACCTL_AP … #define B43_MACCTL_RADIOLOCK … #define B43_MACCTL_BEACPROMISC … #define B43_MACCTL_KEEP_BADPLCP … #define B43_MACCTL_PHY_LOCK … #define B43_MACCTL_KEEP_CTL … #define B43_MACCTL_KEEP_BAD … #define B43_MACCTL_PROMISC … #define B43_MACCTL_HWPS … #define B43_MACCTL_AWAKE … #define B43_MACCTL_CLOSEDNET … #define B43_MACCTL_TBTTHOLD … #define B43_MACCTL_DISCTXSTAT … #define B43_MACCTL_DISCPMQ … #define B43_MACCTL_GMODE … /* MAC Command bitfield */ #define B43_MACCMD_BEACON0_VALID … #define B43_MACCMD_BEACON1_VALID … #define B43_MACCMD_DFQ_VALID … #define B43_MACCMD_CCA … #define B43_MACCMD_BGNOISE … /* B43_MMIO_PSM_PHY_HDR bits */ #define B43_PSM_HDR_MAC_PHY_RESET … #define B43_PSM_HDR_MAC_PHY_CLOCK_EN … #define B43_PSM_HDR_MAC_PHY_FORCE_CLK … /* See BCMA_CLKCTLST_EXTRESREQ and BCMA_CLKCTLST_EXTRESST */ #define B43_BCMA_CLKCTLST_80211_PLL_REQ … #define B43_BCMA_CLKCTLST_PHY_PLL_REQ … #define B43_BCMA_CLKCTLST_80211_PLL_ST … #define B43_BCMA_CLKCTLST_PHY_PLL_ST … /* BCMA 802.11 core specific IO Control (BCMA_IOCTL) flags */ #define B43_BCMA_IOCTL_PHY_CLKEN … #define B43_BCMA_IOCTL_PHY_RESET … #define B43_BCMA_IOCTL_MACPHYCLKEN … #define B43_BCMA_IOCTL_PLLREFSEL … #define B43_BCMA_IOCTL_PHY_BW … #define B43_BCMA_IOCTL_PHY_BW_10MHZ … #define B43_BCMA_IOCTL_PHY_BW_20MHZ … #define B43_BCMA_IOCTL_PHY_BW_40MHZ … #define B43_BCMA_IOCTL_PHY_BW_80MHZ … #define B43_BCMA_IOCTL_DAC … #define B43_BCMA_IOCTL_GMODE … /* BCMA 802.11 core specific IO status (BCMA_IOST) flags */ #define B43_BCMA_IOST_2G_PHY … #define B43_BCMA_IOST_5G_PHY … #define B43_BCMA_IOST_FASTCLKA … #define B43_BCMA_IOST_DUALB_PHY … /* 802.11 core specific TM State Low (SSB_TMSLOW) flags */ #define B43_TMSLOW_GMODE … #define B43_TMSLOW_PHY_BANDWIDTH … #define B43_TMSLOW_PHY_BANDWIDTH_10MHZ … #define B43_TMSLOW_PHY_BANDWIDTH_20MHZ … #define B43_TMSLOW_PHY_BANDWIDTH_40MHZ … #define B43_TMSLOW_PLLREFSEL … #define B43_TMSLOW_MACPHYCLKEN … #define B43_TMSLOW_PHYRESET … #define B43_TMSLOW_PHYCLKEN … /* 802.11 core specific TM State High (SSB_TMSHIGH) flags */ #define B43_TMSHIGH_DUALBAND_PHY … #define B43_TMSHIGH_FCLOCK … #define B43_TMSHIGH_HAVE_5GHZ_PHY … #define B43_TMSHIGH_HAVE_2GHZ_PHY … /* Generic-Interrupt reasons. */ #define B43_IRQ_MAC_SUSPENDED … #define B43_IRQ_BEACON … #define B43_IRQ_TBTT_INDI … #define B43_IRQ_BEACON_TX_OK … #define B43_IRQ_BEACON_CANCEL … #define B43_IRQ_ATIM_END … #define B43_IRQ_PMQ … #define B43_IRQ_PIO_WORKAROUND … #define B43_IRQ_MAC_TXERR … #define B43_IRQ_PHY_TXERR … #define B43_IRQ_PMEVENT … #define B43_IRQ_TIMER0 … #define B43_IRQ_TIMER1 … #define B43_IRQ_DMA … #define B43_IRQ_TXFIFO_FLUSH_OK … #define B43_IRQ_CCA_MEASURE_OK … #define B43_IRQ_NOISESAMPLE_OK … #define B43_IRQ_UCODE_DEBUG … #define B43_IRQ_RFKILL … #define B43_IRQ_TX_OK … #define B43_IRQ_PHY_G_CHANGED … #define B43_IRQ_TIMEOUT … #define B43_IRQ_ALL … #define B43_IRQ_MASKTEMPLATE … /* The firmware register to fetch the debug-IRQ reason from. */ #define B43_DEBUGIRQ_REASON_REG … /* Debug-IRQ reasons. */ #define B43_DEBUGIRQ_PANIC … #define B43_DEBUGIRQ_DUMP_SHM … #define B43_DEBUGIRQ_DUMP_REGS … #define B43_DEBUGIRQ_MARKER … #define B43_DEBUGIRQ_ACK … /* The firmware register that contains the "marker" line. */ #define B43_MARKER_ID_REG … #define B43_MARKER_LINE_REG … /* The firmware register to fetch the panic reason from. */ #define B43_FWPANIC_REASON_REG … /* Firmware panic reason codes */ #define B43_FWPANIC_DIE … #define B43_FWPANIC_RESTART … /* The firmware register that contains the watchdog counter. */ #define B43_WATCHDOG_REG … /* Device specific rate values. * The actual values defined here are (rate_in_mbps * 2). * Some code depends on this. Don't change it. */ #define B43_CCK_RATE_1MB … #define B43_CCK_RATE_2MB … #define B43_CCK_RATE_5MB … #define B43_CCK_RATE_11MB … #define B43_OFDM_RATE_6MB … #define B43_OFDM_RATE_9MB … #define B43_OFDM_RATE_12MB … #define B43_OFDM_RATE_18MB … #define B43_OFDM_RATE_24MB … #define B43_OFDM_RATE_36MB … #define B43_OFDM_RATE_48MB … #define B43_OFDM_RATE_54MB … /* Convert a b43 rate value to a rate in 100kbps */ #define B43_RATE_TO_BASE100KBPS(rate) … #define B43_DEFAULT_SHORT_RETRY_LIMIT … #define B43_DEFAULT_LONG_RETRY_LIMIT … #define B43_PHY_TX_BADNESS_LIMIT … /* Max size of a security key */ #define B43_SEC_KEYSIZE … /* Max number of group keys */ #define B43_NR_GROUP_KEYS … /* Max number of pairwise keys */ #define B43_NR_PAIRWISE_KEYS … /* Security algorithms. */ enum { … }; struct b43_dmaring; /* The firmware file header */ #define B43_FW_TYPE_UCODE … #define B43_FW_TYPE_PCM … #define B43_FW_TYPE_IV … struct b43_fw_header { … } __packed; /* Initial Value file format */ #define B43_IV_OFFSET_MASK … #define B43_IV_32BIT … struct b43_iv { … } __packed; /* Data structures for DMA transmission, per 80211 core. */ struct b43_dma { … }; struct b43_pio_txqueue; struct b43_pio_rxqueue; /* Data structures for PIO transmission, per 80211 core. */ struct b43_pio { … }; /* Context information for a noise calculation (Link Quality). */ struct b43_noise_calculation { … }; struct b43_stats { … }; struct b43_key { … }; /* SHM offsets to the QOS data structures for the 4 different queues. */ #define B43_QOS_QUEUE_NUM … #define B43_QOS_PARAMS(queue) … #define B43_QOS_BACKGROUND … #define B43_QOS_BESTEFFORT … #define B43_QOS_VIDEO … #define B43_QOS_VOICE … /* QOS parameter hardware data structure offsets. */ #define B43_NR_QOSPARAMS … enum { … }; /* QOS parameters for a queue. */ struct b43_qos_params { … }; struct b43_wl; /* The type of the firmware file. */ enum b43_firmware_file_type { … }; /* Context data for fetching firmware. */ struct b43_request_fw_context { … }; /* In-memory representation of a cached microcode file. */ struct b43_firmware_file { … }; enum b43_firmware_hdr_format { … }; /* Pointers to the firmware data and meta information about it. */ struct b43_firmware { … }; enum b43_band { … }; /* Device (802.11 core) initialization status. */ enum { … }; #define b43_status(wldev) … #define b43_set_status(wldev, stat) … /* Data structure for one wireless device (802.11 core) */ struct b43_wldev { … }; /* Data structure for the WLAN parts (802.11 cores) of the b43 chip. */ struct b43_wl { … }; static inline struct b43_wl *hw_to_b43_wl(struct ieee80211_hw *hw) { … } static inline struct b43_wldev *dev_to_b43_wldev(struct device *dev) { … } /* Is the device operating in a specified mode (NL80211_IFTYPE_XXX). */ static inline int b43_is_mode(struct b43_wl *wl, int type) { … } /** * b43_current_band - Returns the currently used band. * Returns one of NL80211_BAND_2GHZ and NL80211_BAND_5GHZ. */ static inline enum nl80211_band b43_current_band(struct b43_wl *wl) { … } static inline int b43_bus_may_powerdown(struct b43_wldev *wldev) { … } static inline int b43_bus_powerup(struct b43_wldev *wldev, bool dynamic_pctl) { … } static inline int b43_device_is_enabled(struct b43_wldev *wldev) { … } static inline void b43_device_enable(struct b43_wldev *wldev, u32 core_specific_flags) { … } static inline void b43_device_disable(struct b43_wldev *wldev, u32 core_specific_flags) { … } static inline u16 b43_read16(struct b43_wldev *dev, u16 offset) { … } static inline void b43_write16(struct b43_wldev *dev, u16 offset, u16 value) { … } /* To optimize this check for flush_writes on BCM47XX_BCMA only. */ static inline void b43_write16f(struct b43_wldev *dev, u16 offset, u16 value) { … } static inline void b43_maskset16(struct b43_wldev *dev, u16 offset, u16 mask, u16 set) { … } static inline u32 b43_read32(struct b43_wldev *dev, u16 offset) { … } static inline void b43_write32(struct b43_wldev *dev, u16 offset, u32 value) { … } static inline void b43_maskset32(struct b43_wldev *dev, u16 offset, u32 mask, u32 set) { … } static inline void b43_block_read(struct b43_wldev *dev, void *buffer, size_t count, u16 offset, u8 reg_width) { … } static inline void b43_block_write(struct b43_wldev *dev, const void *buffer, size_t count, u16 offset, u8 reg_width) { … } static inline bool b43_using_pio_transfers(struct b43_wldev *dev) { … } static inline void b43_wake_queue(struct b43_wldev *dev, int queue_prio) { … } static inline void b43_stop_queue(struct b43_wldev *dev, int queue_prio) { … } /* Message printing */ __printf(2, 3) void b43info(struct b43_wl *wl, const char *fmt, ...); __printf(2, 3) void b43err(struct b43_wl *wl, const char *fmt, ...); __printf(2, 3) void b43warn(struct b43_wl *wl, const char *fmt, ...); __printf(2, 3) void b43dbg(struct b43_wl *wl, const char *fmt, ...); /* A WARN_ON variant that vanishes when b43 debugging is disabled. * This _also_ evaluates the arg with debugging disabled. */ #if B43_DEBUG #define B43_WARN_ON(x) … #else static inline bool __b43_warn_on_dummy(bool x) { return x; } #define B43_WARN_ON … #endif /* Convert an integer to a Q5.2 value */ #define INT_TO_Q52(i) … /* Convert a Q5.2 value to an integer (precision loss!) */ #define Q52_TO_INT(q52) … /* Macros for printing a value in Q5.2 format */ #define Q52_FMT … #define Q52_ARG(q52) … #endif /* B43_H_ */
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