/* SPDX-License-Identifier: GPL-2.0 */ #ifndef B43_DMA_H_ #define B43_DMA_H_ #include <linux/err.h> #include "b43.h" /* DMA-Interrupt reasons. */ #define B43_DMAIRQ_FATALMASK … #define B43_DMAIRQ_RDESC_UFLOW … #define B43_DMAIRQ_RX_DONE … /*** 32-bit DMA Engine. ***/ /* 32-bit DMA controller registers. */ #define B43_DMA32_TXCTL … #define B43_DMA32_TXENABLE … #define B43_DMA32_TXSUSPEND … #define B43_DMA32_TXLOOPBACK … #define B43_DMA32_TXFLUSH … #define B43_DMA32_TXPARITYDISABLE … #define B43_DMA32_TXADDREXT_MASK … #define B43_DMA32_TXADDREXT_SHIFT … #define B43_DMA32_TXRING … #define B43_DMA32_TXINDEX … #define B43_DMA32_TXSTATUS … #define B43_DMA32_TXDPTR … #define B43_DMA32_TXSTATE … #define B43_DMA32_TXSTAT_DISABLED … #define B43_DMA32_TXSTAT_ACTIVE … #define B43_DMA32_TXSTAT_IDLEWAIT … #define B43_DMA32_TXSTAT_STOPPED … #define B43_DMA32_TXSTAT_SUSP … #define B43_DMA32_TXERROR … #define B43_DMA32_TXERR_NOERR … #define B43_DMA32_TXERR_PROT … #define B43_DMA32_TXERR_UNDERRUN … #define B43_DMA32_TXERR_BUFREAD … #define B43_DMA32_TXERR_DESCREAD … #define B43_DMA32_TXACTIVE … #define B43_DMA32_RXCTL … #define B43_DMA32_RXENABLE … #define B43_DMA32_RXFROFF_MASK … #define B43_DMA32_RXFROFF_SHIFT … #define B43_DMA32_RXDIRECTFIFO … #define B43_DMA32_RXPARITYDISABLE … #define B43_DMA32_RXADDREXT_MASK … #define B43_DMA32_RXADDREXT_SHIFT … #define B43_DMA32_RXRING … #define B43_DMA32_RXINDEX … #define B43_DMA32_RXSTATUS … #define B43_DMA32_RXDPTR … #define B43_DMA32_RXSTATE … #define B43_DMA32_RXSTAT_DISABLED … #define B43_DMA32_RXSTAT_ACTIVE … #define B43_DMA32_RXSTAT_IDLEWAIT … #define B43_DMA32_RXSTAT_STOPPED … #define B43_DMA32_RXERROR … #define B43_DMA32_RXERR_NOERR … #define B43_DMA32_RXERR_PROT … #define B43_DMA32_RXERR_OVERFLOW … #define B43_DMA32_RXERR_BUFWRITE … #define B43_DMA32_RXERR_DESCREAD … #define B43_DMA32_RXACTIVE … /* 32-bit DMA descriptor. */ struct b43_dmadesc32 { … } __packed; #define B43_DMA32_DCTL_BYTECNT … #define B43_DMA32_DCTL_ADDREXT_MASK … #define B43_DMA32_DCTL_ADDREXT_SHIFT … #define B43_DMA32_DCTL_DTABLEEND … #define B43_DMA32_DCTL_IRQ … #define B43_DMA32_DCTL_FRAMEEND … #define B43_DMA32_DCTL_FRAMESTART … /*** 64-bit DMA Engine. ***/ /* 64-bit DMA controller registers. */ #define B43_DMA64_TXCTL … #define B43_DMA64_TXENABLE … #define B43_DMA64_TXSUSPEND … #define B43_DMA64_TXLOOPBACK … #define B43_DMA64_TXFLUSH … #define B43_DMA64_TXPARITYDISABLE … #define B43_DMA64_TXADDREXT_MASK … #define B43_DMA64_TXADDREXT_SHIFT … #define B43_DMA64_TXINDEX … #define B43_DMA64_TXRINGLO … #define B43_DMA64_TXRINGHI … #define B43_DMA64_TXSTATUS … #define B43_DMA64_TXSTATDPTR … #define B43_DMA64_TXSTAT … #define B43_DMA64_TXSTAT_DISABLED … #define B43_DMA64_TXSTAT_ACTIVE … #define B43_DMA64_TXSTAT_IDLEWAIT … #define B43_DMA64_TXSTAT_STOPPED … #define B43_DMA64_TXSTAT_SUSP … #define B43_DMA64_TXERROR … #define B43_DMA64_TXERRDPTR … #define B43_DMA64_TXERR … #define B43_DMA64_TXERR_NOERR … #define B43_DMA64_TXERR_PROT … #define B43_DMA64_TXERR_UNDERRUN … #define B43_DMA64_TXERR_TRANSFER … #define B43_DMA64_TXERR_DESCREAD … #define B43_DMA64_TXERR_CORE … #define B43_DMA64_RXCTL … #define B43_DMA64_RXENABLE … #define B43_DMA64_RXFROFF_MASK … #define B43_DMA64_RXFROFF_SHIFT … #define B43_DMA64_RXDIRECTFIFO … #define B43_DMA64_RXPARITYDISABLE … #define B43_DMA64_RXADDREXT_MASK … #define B43_DMA64_RXADDREXT_SHIFT … #define B43_DMA64_RXINDEX … #define B43_DMA64_RXRINGLO … #define B43_DMA64_RXRINGHI … #define B43_DMA64_RXSTATUS … #define B43_DMA64_RXSTATDPTR … #define B43_DMA64_RXSTAT … #define B43_DMA64_RXSTAT_DISABLED … #define B43_DMA64_RXSTAT_ACTIVE … #define B43_DMA64_RXSTAT_IDLEWAIT … #define B43_DMA64_RXSTAT_STOPPED … #define B43_DMA64_RXSTAT_SUSP … #define B43_DMA64_RXERROR … #define B43_DMA64_RXERRDPTR … #define B43_DMA64_RXERR … #define B43_DMA64_RXERR_NOERR … #define B43_DMA64_RXERR_PROT … #define B43_DMA64_RXERR_UNDERRUN … #define B43_DMA64_RXERR_TRANSFER … #define B43_DMA64_RXERR_DESCREAD … #define B43_DMA64_RXERR_CORE … /* 64-bit DMA descriptor. */ struct b43_dmadesc64 { … } __packed; #define B43_DMA64_DCTL0_DTABLEEND … #define B43_DMA64_DCTL0_IRQ … #define B43_DMA64_DCTL0_FRAMEEND … #define B43_DMA64_DCTL0_FRAMESTART … #define B43_DMA64_DCTL1_BYTECNT … #define B43_DMA64_DCTL1_ADDREXT_MASK … #define B43_DMA64_DCTL1_ADDREXT_SHIFT … struct b43_dmadesc_generic { … } __packed; /* Misc DMA constants */ #define B43_DMA32_RINGMEMSIZE … #define B43_DMA64_RINGMEMSIZE … /* Offset of frame with actual data */ #define B43_DMA0_RX_FW598_FO … #define B43_DMA0_RX_FW351_FO … /* DMA engine tuning knobs */ #define B43_TXRING_SLOTS … #define B43_RXRING_SLOTS … #define B43_DMA0_RX_FW598_BUFSIZE … #define B43_DMA0_RX_FW351_BUFSIZE … /* Pointer poison */ #define B43_DMA_PTR_POISON … #define b43_dma_ptr_is_poisoned(ptr) … struct sk_buff; struct b43_private; struct b43_txstatus; struct b43_dmadesc_meta { … }; struct b43_dmaring; /* Lowlevel DMA operations that differ between 32bit and 64bit DMA. */ struct b43_dma_ops { … }; enum b43_dmatype { … }; enum b43_addrtype { … }; struct b43_dmaring { … }; static inline u32 b43_dma_read(struct b43_dmaring *ring, u16 offset) { … } static inline void b43_dma_write(struct b43_dmaring *ring, u16 offset, u32 value) { … } int b43_dma_init(struct b43_wldev *dev); void b43_dma_free(struct b43_wldev *dev); void b43_dma_tx_suspend(struct b43_wldev *dev); void b43_dma_tx_resume(struct b43_wldev *dev); int b43_dma_tx(struct b43_wldev *dev, struct sk_buff *skb); void b43_dma_handle_txstatus(struct b43_wldev *dev, const struct b43_txstatus *status); void b43_dma_handle_rx_overflow(struct b43_dmaring *ring); void b43_dma_rx(struct b43_dmaring *ring); void b43_dma_direct_fifo_rx(struct b43_wldev *dev, unsigned int engine_index, bool enable); #endif /* B43_DMA_H_ */
Codebase Browser
linux