/* SPDX-License-Identifier: GPL-2.0 */ #ifndef B43_PHY_HT_H_ #define B43_PHY_HT_H_ #include "phy_common.h" #define B43_PHY_HT_BBCFG … #define B43_PHY_HT_BBCFG_RSTCCA … #define B43_PHY_HT_BBCFG_RSTRX … #define B43_PHY_HT_BANDCTL … #define B43_PHY_HT_BANDCTL_5GHZ … #define B43_PHY_HT_TABLE_ADDR … #define B43_PHY_HT_TABLE_DATALO … #define B43_PHY_HT_TABLE_DATAHI … #define B43_PHY_HT_CLASS_CTL … #define B43_PHY_HT_CLASS_CTL_CCK_EN … #define B43_PHY_HT_CLASS_CTL_OFDM_EN … #define B43_PHY_HT_CLASS_CTL_WAITED_EN … #define B43_PHY_HT_IQLOCAL_CMDGCTL … #define B43_PHY_HT_SAMP_CMD … #define B43_PHY_HT_SAMP_CMD_STOP … #define B43_PHY_HT_SAMP_LOOP_CNT … #define B43_PHY_HT_SAMP_WAIT_CNT … #define B43_PHY_HT_SAMP_DEP_CNT … #define B43_PHY_HT_SAMP_STAT … #define B43_PHY_HT_EST_PWR_C1 … #define B43_PHY_HT_EST_PWR_C2 … #define B43_PHY_HT_EST_PWR_C3 … #define B43_PHY_HT_TSSIMODE … #define B43_PHY_HT_TSSIMODE_EN … #define B43_PHY_HT_TSSIMODE_PDEN … #define B43_PHY_HT_BW1 … #define B43_PHY_HT_BW2 … #define B43_PHY_HT_BW3 … #define B43_PHY_HT_BW4 … #define B43_PHY_HT_BW5 … #define B43_PHY_HT_BW6 … #define B43_PHY_HT_TXPCTL_CMD_C1 … #define B43_PHY_HT_TXPCTL_CMD_C1_INIT … #define B43_PHY_HT_TXPCTL_CMD_C1_COEFF … #define B43_PHY_HT_TXPCTL_CMD_C1_HWPCTLEN … #define B43_PHY_HT_TXPCTL_CMD_C1_PCTLEN … #define B43_PHY_HT_TXPCTL_N … #define B43_PHY_HT_TXPCTL_N_TSSID … #define B43_PHY_HT_TXPCTL_N_TSSID_SHIFT … #define B43_PHY_HT_TXPCTL_N_NPTIL2 … #define B43_PHY_HT_TXPCTL_N_NPTIL2_SHIFT … #define B43_PHY_HT_TXPCTL_IDLE_TSSI … #define B43_PHY_HT_TXPCTL_IDLE_TSSI_C1 … #define B43_PHY_HT_TXPCTL_IDLE_TSSI_C1_SHIFT … #define B43_PHY_HT_TXPCTL_IDLE_TSSI_C2 … #define B43_PHY_HT_TXPCTL_IDLE_TSSI_C2_SHIFT … #define B43_PHY_HT_TXPCTL_IDLE_TSSI_BINF … #define B43_PHY_HT_TXPCTL_TARG_PWR … #define B43_PHY_HT_TXPCTL_TARG_PWR_C1 … #define B43_PHY_HT_TXPCTL_TARG_PWR_C1_SHIFT … #define B43_PHY_HT_TXPCTL_TARG_PWR_C2 … #define B43_PHY_HT_TXPCTL_TARG_PWR_C2_SHIFT … #define B43_PHY_HT_TX_PCTL_STATUS_C1 … #define B43_PHY_HT_TX_PCTL_STATUS_C2 … #define B43_PHY_HT_TXPCTL_CMD_C2 … #define B43_PHY_HT_TXPCTL_CMD_C2_INIT … #define B43_PHY_HT_RSSI_C1 … #define B43_PHY_HT_RSSI_C2 … #define B43_PHY_HT_RSSI_C3 … #define B43_PHY_HT_C1_CLIP1THRES … #define B43_PHY_HT_C2_CLIP1THRES … #define B43_PHY_HT_C3_CLIP1THRES … #define B43_PHY_HT_RF_SEQ_MODE … #define B43_PHY_HT_RF_SEQ_MODE_CA_OVER … #define B43_PHY_HT_RF_SEQ_MODE_TR_OVER … #define B43_PHY_HT_RF_SEQ_TRIG … #define B43_PHY_HT_RF_SEQ_TRIG_RX2TX … #define B43_PHY_HT_RF_SEQ_TRIG_TX2RX … #define B43_PHY_HT_RF_SEQ_TRIG_UPGH … #define B43_PHY_HT_RF_SEQ_TRIG_UPGL … #define B43_PHY_HT_RF_SEQ_TRIG_UPGU … #define B43_PHY_HT_RF_SEQ_TRIG_RST2RX … #define B43_PHY_HT_RF_SEQ_STATUS … /* Values for the status are the same as for the trigger */ #define B43_PHY_HT_RF_CTL_CMD … #define B43_PHY_HT_RF_CTL_CMD_FORCE … #define B43_PHY_HT_RF_CTL_CMD_CHIP0_PU … #define B43_PHY_HT_RF_CTL_INT_C1 … #define B43_PHY_HT_RF_CTL_INT_C2 … #define B43_PHY_HT_RF_CTL_INT_C3 … #define B43_PHY_HT_AFE_C1_OVER … #define B43_PHY_HT_AFE_C1 … #define B43_PHY_HT_AFE_C2_OVER … #define B43_PHY_HT_AFE_C2 … #define B43_PHY_HT_AFE_C3_OVER … #define B43_PHY_HT_AFE_C3 … #define B43_PHY_HT_TXPCTL_CMD_C3 … #define B43_PHY_HT_TXPCTL_CMD_C3_INIT … #define B43_PHY_HT_TXPCTL_IDLE_TSSI2 … #define B43_PHY_HT_TXPCTL_IDLE_TSSI2_C3 … #define B43_PHY_HT_TXPCTL_IDLE_TSSI2_C3_SHIFT … #define B43_PHY_HT_TXPCTL_TARG_PWR2 … #define B43_PHY_HT_TXPCTL_TARG_PWR2_C3 … #define B43_PHY_HT_TXPCTL_TARG_PWR2_C3_SHIFT … #define B43_PHY_HT_TX_PCTL_STATUS_C3 … #define B43_PHY_B_BBCFG … #define B43_PHY_B_BBCFG_RSTCCA … #define B43_PHY_B_BBCFG_RSTRX … #define B43_PHY_HT_TEST … /* Values for PHY registers used on channel switching */ struct b43_phy_ht_channeltab_e_phy { … }; struct b43_phy_ht { … }; struct b43_phy_operations; extern const struct b43_phy_operations b43_phyops_ht; #endif /* B43_PHY_HT_H_ */
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