/* SPDX-License-Identifier: GPL-2.0 */ #ifndef B43_XMIT_H_ #define B43_XMIT_H_ #include "main.h" #include <net/mac80211.h> #define _b43_declare_plcp_hdr … /* struct b43_plcp_hdr4 */ _b43_declare_plcp_hdr … } ; /* struct b43_plcp_hdr6 */ _b43_declare_plcp_hdr … } ; #undef _b43_declare_plcp_hdr /* TX header for v4 firmware */ struct b43_txhdr { … } __packed; struct b43_tx_legacy_rate_phy_ctl_entry { … }; /* MAC TX control */ #define B43_TXH_MAC_RTS_FB_SHORTPRMBL … #define B43_TXH_MAC_RTS_SHORTPRMBL … #define B43_TXH_MAC_FB_SHORTPRMBL … #define B43_TXH_MAC_USEFBR … #define B43_TXH_MAC_KEYIDX … #define B43_TXH_MAC_KEYIDX_SHIFT … #define B43_TXH_MAC_ALT_TXPWR … #define B43_TXH_MAC_KEYALG … #define B43_TXH_MAC_KEYALG_SHIFT … #define B43_TXH_MAC_AMIC … #define B43_TXH_MAC_RIFS … #define B43_TXH_MAC_LIFETIME … #define B43_TXH_MAC_FRAMEBURST … #define B43_TXH_MAC_SENDCTS … #define B43_TXH_MAC_AMPDU … #define B43_TXH_MAC_AMPDU_MPDU … #define B43_TXH_MAC_AMPDU_FIRST … #define B43_TXH_MAC_AMPDU_INTER … #define B43_TXH_MAC_AMPDU_LAST … #define B43_TXH_MAC_40MHZ … #define B43_TXH_MAC_5GHZ … #define B43_TXH_MAC_DFCS … #define B43_TXH_MAC_IGNPMQ … #define B43_TXH_MAC_HWSEQ … #define B43_TXH_MAC_STMSDU … #define B43_TXH_MAC_SENDRTS … #define B43_TXH_MAC_LONGFRAME … #define B43_TXH_MAC_ACK … /* Extra Frame Types */ #define B43_TXH_EFT_FB … #define B43_TXH_EFT_FB_CCK … #define B43_TXH_EFT_FB_OFDM … #define B43_TXH_EFT_FB_HT … #define B43_TXH_EFT_FB_VHT … #define B43_TXH_EFT_RTS … #define B43_TXH_EFT_RTS_CCK … #define B43_TXH_EFT_RTS_OFDM … #define B43_TXH_EFT_RTS_HT … #define B43_TXH_EFT_RTS_VHT … #define B43_TXH_EFT_RTSFB … #define B43_TXH_EFT_RTSFB_CCK … #define B43_TXH_EFT_RTSFB_OFDM … #define B43_TXH_EFT_RTSFB_HT … #define B43_TXH_EFT_RTSFB_VHT … /* PHY TX control word */ #define B43_TXH_PHY_ENC … #define B43_TXH_PHY_ENC_CCK … #define B43_TXH_PHY_ENC_OFDM … #define B43_TXH_PHY_ENC_HT … #define B43_TXH_PHY_ENC_VHT … #define B43_TXH_PHY_SHORTPRMBL … #define B43_TXH_PHY_ANT … #define B43_TXH_PHY_ANT0 … #define B43_TXH_PHY_ANT1 … #define B43_TXH_PHY_ANT01AUTO … #define B43_TXH_PHY_ANT2 … #define B43_TXH_PHY_ANT3 … #define B43_TXH_PHY_TXPWR … #define B43_TXH_PHY_TXPWR_SHIFT … /* PHY TX control word 1 */ #define B43_TXH_PHY1_BW … #define B43_TXH_PHY1_BW_10 … #define B43_TXH_PHY1_BW_10U … #define B43_TXH_PHY1_BW_20 … #define B43_TXH_PHY1_BW_20U … #define B43_TXH_PHY1_BW_40 … #define B43_TXH_PHY1_BW_40DUP … #define B43_TXH_PHY1_MODE … #define B43_TXH_PHY1_MODE_SISO … #define B43_TXH_PHY1_MODE_CDD … #define B43_TXH_PHY1_MODE_STBC … #define B43_TXH_PHY1_MODE_SDM … #define B43_TXH_PHY1_CRATE … #define B43_TXH_PHY1_CRATE_1_2 … #define B43_TXH_PHY1_CRATE_2_3 … #define B43_TXH_PHY1_CRATE_3_4 … #define B43_TXH_PHY1_CRATE_4_5 … #define B43_TXH_PHY1_CRATE_5_6 … #define B43_TXH_PHY1_CRATE_7_8 … #define B43_TXH_PHY1_MODUL … #define B43_TXH_PHY1_MODUL_BPSK … #define B43_TXH_PHY1_MODUL_QPSK … #define B43_TXH_PHY1_MODUL_QAM16 … #define B43_TXH_PHY1_MODUL_QAM64 … #define B43_TXH_PHY1_MODUL_QAM256 … static inline size_t b43_txhdr_size(struct b43_wldev *dev) { … } int b43_generate_txhdr(struct b43_wldev *dev, u8 * txhdr, struct sk_buff *skb_frag, struct ieee80211_tx_info *txctl, u16 cookie); /* Transmit Status */ struct b43_txstatus { … }; /* txstatus supp_reason values */ enum { … }; /* Receive header for v4 firmware. */ struct b43_rxhdr_fw4 { … } __packed; /* PHY RX Status 0 */ #define B43_RX_PHYST0_GAINCTL … #define B43_RX_PHYST0_PLCPHCF … #define B43_RX_PHYST0_PLCPFV … #define B43_RX_PHYST0_SHORTPRMBL … #define B43_RX_PHYST0_LCRS … #define B43_RX_PHYST0_ANT … #define B43_RX_PHYST0_UNSRATE … #define B43_RX_PHYST0_CLIP … #define B43_RX_PHYST0_CLIP_SHIFT … #define B43_RX_PHYST0_FTYPE … #define B43_RX_PHYST0_CCK … #define B43_RX_PHYST0_OFDM … #define B43_RX_PHYST0_PRE_N … #define B43_RX_PHYST0_STD_N … /* PHY RX Status 2 */ #define B43_RX_PHYST2_LNAG … #define B43_RX_PHYST2_LNAG_SHIFT … #define B43_RX_PHYST2_PNAG … #define B43_RX_PHYST2_PNAG_SHIFT … #define B43_RX_PHYST2_FOFF … /* PHY RX Status 3 */ #define B43_RX_PHYST3_DIGG … #define B43_RX_PHYST3_DIGG_SHIFT … #define B43_RX_PHYST3_TRSTATE … /* MAC RX Status */ #define B43_RX_MAC_RXST_VALID … #define B43_RX_MAC_TKIP_MICERR … #define B43_RX_MAC_TKIP_MICATT … #define B43_RX_MAC_AGGTYPE … #define B43_RX_MAC_AGGTYPE_SHIFT … #define B43_RX_MAC_AMSDU … #define B43_RX_MAC_BEACONSENT … #define B43_RX_MAC_KEYIDX … #define B43_RX_MAC_KEYIDX_SHIFT … #define B43_RX_MAC_DECERR … #define B43_RX_MAC_DEC … #define B43_RX_MAC_PADDING … #define B43_RX_MAC_RESP … #define B43_RX_MAC_FCSERR … /* RX channel */ #define B43_RX_CHAN_40MHZ … #define B43_RX_CHAN_5GHZ … #define B43_RX_CHAN_ID … #define B43_RX_CHAN_ID_SHIFT … #define B43_RX_CHAN_PHYTYPE … u8 b43_plcp_get_ratecode_cck(const u8 bitrate); u8 b43_plcp_get_ratecode_ofdm(const u8 bitrate); void b43_generate_plcp_hdr(struct b43_plcp_hdr4 *plcp, const u16 octets, const u8 bitrate); void b43_rx(struct b43_wldev *dev, struct sk_buff *skb, const void *_rxhdr); void b43_handle_txstatus(struct b43_wldev *dev, const struct b43_txstatus *status); bool b43_fill_txstatus_report(struct b43_wldev *dev, struct ieee80211_tx_info *report, const struct b43_txstatus *status); void b43_tx_suspend(struct b43_wldev *dev); void b43_tx_resume(struct b43_wldev *dev); /* Helper functions for converting the key-table index from "firmware-format" * to "raw-format" and back. The firmware API changed for this at some revision. * We need to account for that here. */ static inline int b43_new_kidx_api(struct b43_wldev *dev) { … } static inline u8 b43_kidx_to_fw(struct b43_wldev *dev, u8 raw_kidx) { … } static inline u8 b43_kidx_to_raw(struct b43_wldev *dev, u8 firmware_kidx) { … } /* struct b43_private_tx_info - TX info private to b43. * The structure is placed in (struct ieee80211_tx_info *)->rate_driver_data * * @bouncebuffer: DMA Bouncebuffer (if used) */ struct b43_private_tx_info { … }; static inline struct b43_private_tx_info * b43_get_priv_tx_info(struct ieee80211_tx_info *info) { … } #endif /* B43_XMIT_H_ */
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