/* SPDX-License-Identifier: GPL-2.0 */ #ifndef B43legacy_H_ #define B43legacy_H_ #include <linux/hw_random.h> #include <linux/kernel.h> #include <linux/spinlock.h> #include <linux/interrupt.h> #include <linux/stringify.h> #include <linux/netdevice.h> #include <linux/pci.h> #include <linux/atomic.h> #include <linux/io.h> #include <linux/ssb/ssb.h> #include <linux/ssb/ssb_driver_chipcommon.h> #include <linux/completion.h> #include <net/mac80211.h> #include "debugfs.h" #include "leds.h" #include "rfkill.h" #include "phy.h" #define B43legacy_IRQWAIT_MAX_RETRIES … /* MMIO offsets */ #define B43legacy_MMIO_DMA0_REASON … #define B43legacy_MMIO_DMA0_IRQ_MASK … #define B43legacy_MMIO_DMA1_REASON … #define B43legacy_MMIO_DMA1_IRQ_MASK … #define B43legacy_MMIO_DMA2_REASON … #define B43legacy_MMIO_DMA2_IRQ_MASK … #define B43legacy_MMIO_DMA3_REASON … #define B43legacy_MMIO_DMA3_IRQ_MASK … #define B43legacy_MMIO_DMA4_REASON … #define B43legacy_MMIO_DMA4_IRQ_MASK … #define B43legacy_MMIO_DMA5_REASON … #define B43legacy_MMIO_DMA5_IRQ_MASK … #define B43legacy_MMIO_MACCTL … #define B43legacy_MMIO_MACCMD … #define B43legacy_MMIO_GEN_IRQ_REASON … #define B43legacy_MMIO_GEN_IRQ_MASK … #define B43legacy_MMIO_RAM_CONTROL … #define B43legacy_MMIO_RAM_DATA … #define B43legacy_MMIO_PS_STATUS … #define B43legacy_MMIO_RADIO_HWENABLED_HI … #define B43legacy_MMIO_SHM_CONTROL … #define B43legacy_MMIO_SHM_DATA … #define B43legacy_MMIO_SHM_DATA_UNALIGNED … #define B43legacy_MMIO_XMITSTAT_0 … #define B43legacy_MMIO_XMITSTAT_1 … #define B43legacy_MMIO_REV3PLUS_TSF_LOW … #define B43legacy_MMIO_REV3PLUS_TSF_HIGH … #define B43legacy_MMIO_TSF_CFP_REP … #define B43legacy_MMIO_TSF_CFP_START … /* 32-bit DMA */ #define B43legacy_MMIO_DMA32_BASE0 … #define B43legacy_MMIO_DMA32_BASE1 … #define B43legacy_MMIO_DMA32_BASE2 … #define B43legacy_MMIO_DMA32_BASE3 … #define B43legacy_MMIO_DMA32_BASE4 … #define B43legacy_MMIO_DMA32_BASE5 … /* 64-bit DMA */ #define B43legacy_MMIO_DMA64_BASE0 … #define B43legacy_MMIO_DMA64_BASE1 … #define B43legacy_MMIO_DMA64_BASE2 … #define B43legacy_MMIO_DMA64_BASE3 … #define B43legacy_MMIO_DMA64_BASE4 … #define B43legacy_MMIO_DMA64_BASE5 … /* PIO */ #define B43legacy_MMIO_PIO1_BASE … #define B43legacy_MMIO_PIO2_BASE … #define B43legacy_MMIO_PIO3_BASE … #define B43legacy_MMIO_PIO4_BASE … #define B43legacy_MMIO_PHY_VER … #define B43legacy_MMIO_PHY_RADIO … #define B43legacy_MMIO_PHY0 … #define B43legacy_MMIO_ANTENNA … #define B43legacy_MMIO_CHANNEL … #define B43legacy_MMIO_CHANNEL_EXT … #define B43legacy_MMIO_RADIO_CONTROL … #define B43legacy_MMIO_RADIO_DATA_HIGH … #define B43legacy_MMIO_RADIO_DATA_LOW … #define B43legacy_MMIO_PHY_CONTROL … #define B43legacy_MMIO_PHY_DATA … #define B43legacy_MMIO_MACFILTER_CONTROL … #define B43legacy_MMIO_MACFILTER_DATA … #define B43legacy_MMIO_RCMTA_COUNT … #define B43legacy_MMIO_RADIO_HWENABLED_LO … #define B43legacy_MMIO_GPIO_CONTROL … #define B43legacy_MMIO_GPIO_MASK … #define B43legacy_MMIO_TSF_CFP_PRETBTT … #define B43legacy_MMIO_TSF_0 … #define B43legacy_MMIO_TSF_1 … #define B43legacy_MMIO_TSF_2 … #define B43legacy_MMIO_TSF_3 … #define B43legacy_MMIO_RNG … #define B43legacy_MMIO_POWERUP_DELAY … /* SPROM boardflags_lo values */ #define B43legacy_BFL_PACTRL … #define B43legacy_BFL_RSSI … #define B43legacy_BFL_EXTLNA … /* GPIO register offset, in both ChipCommon and PCI core. */ #define B43legacy_GPIO_CONTROL … /* SHM Routing */ #define B43legacy_SHM_SHARED … #define B43legacy_SHM_WIRELESS … #define B43legacy_SHM_HW … #define B43legacy_SHM_UCODE … /* SHM Routing modifiers */ #define B43legacy_SHM_AUTOINC_R … #define B43legacy_SHM_AUTOINC_W … #define B43legacy_SHM_AUTOINC_RW … /* Misc SHM_SHARED offsets */ #define B43legacy_SHM_SH_WLCOREREV … #define B43legacy_SHM_SH_HOSTFLO … #define B43legacy_SHM_SH_HOSTFHI … /* SHM_SHARED crypto engine */ #define B43legacy_SHM_SH_KEYIDXBLOCK … /* SHM_SHARED beacon/AP variables */ #define B43legacy_SHM_SH_DTIMP … #define B43legacy_SHM_SH_BTL0 … #define B43legacy_SHM_SH_BTL1 … #define B43legacy_SHM_SH_BTSFOFF … #define B43legacy_SHM_SH_TIMPOS … #define B43legacy_SHM_SH_BEACPHYCTL … /* SHM_SHARED ACK/CTS control */ #define B43legacy_SHM_SH_ACKCTSPHYCTL … /* SHM_SHARED probe response variables */ #define B43legacy_SHM_SH_PRTLEN … #define B43legacy_SHM_SH_PRMAXTIME … #define B43legacy_SHM_SH_PRPHYCTL … /* SHM_SHARED rate tables */ #define B43legacy_SHM_SH_OFDMDIRECT … #define B43legacy_SHM_SH_OFDMBASIC … #define B43legacy_SHM_SH_CCKDIRECT … #define B43legacy_SHM_SH_CCKBASIC … /* SHM_SHARED microcode soft registers */ #define B43legacy_SHM_SH_UCODEREV … #define B43legacy_SHM_SH_UCODEPATCH … #define B43legacy_SHM_SH_UCODEDATE … #define B43legacy_SHM_SH_UCODETIME … #define B43legacy_SHM_SH_SPUWKUP … #define B43legacy_SHM_SH_PRETBTT … #define B43legacy_UCODEFLAGS_OFFSET … /* Hardware Radio Enable masks */ #define B43legacy_MMIO_RADIO_HWENABLED_HI_MASK … #define B43legacy_MMIO_RADIO_HWENABLED_LO_MASK … /* HostFlags. See b43legacy_hf_read/write() */ #define B43legacy_HF_SYMW … #define B43legacy_HF_GDCW … #define B43legacy_HF_OFDMPABOOST … #define B43legacy_HF_EDCF … /* MacFilter offsets. */ #define B43legacy_MACFILTER_SELF … #define B43legacy_MACFILTER_BSSID … #define B43legacy_MACFILTER_MAC … /* PHYVersioning */ #define B43legacy_PHYTYPE_B … #define B43legacy_PHYTYPE_G … /* PHYRegisters */ #define B43legacy_PHY_G_LO_CONTROL … #define B43legacy_PHY_ILT_G_CTRL … #define B43legacy_PHY_ILT_G_DATA1 … #define B43legacy_PHY_ILT_G_DATA2 … #define B43legacy_PHY_G_PCTL … #define B43legacy_PHY_RADIO_BITFIELD … #define B43legacy_PHY_G_CRS … #define B43legacy_PHY_NRSSILT_CTRL … #define B43legacy_PHY_NRSSILT_DATA … /* RadioRegisters */ #define B43legacy_RADIOCTL_ID … /* MAC Control bitfield */ #define B43legacy_MACCTL_ENABLED … #define B43legacy_MACCTL_PSM_RUN … #define B43legacy_MACCTL_PSM_JMP0 … #define B43legacy_MACCTL_SHM_ENABLED … #define B43legacy_MACCTL_IHR_ENABLED … #define B43legacy_MACCTL_BE … #define B43legacy_MACCTL_INFRA … #define B43legacy_MACCTL_AP … #define B43legacy_MACCTL_RADIOLOCK … #define B43legacy_MACCTL_BEACPROMISC … #define B43legacy_MACCTL_KEEP_BADPLCP … #define B43legacy_MACCTL_KEEP_CTL … #define B43legacy_MACCTL_KEEP_BAD … #define B43legacy_MACCTL_PROMISC … #define B43legacy_MACCTL_HWPS … #define B43legacy_MACCTL_AWAKE … #define B43legacy_MACCTL_TBTTHOLD … #define B43legacy_MACCTL_GMODE … /* MAC Command bitfield */ #define B43legacy_MACCMD_BEACON0_VALID … #define B43legacy_MACCMD_BEACON1_VALID … #define B43legacy_MACCMD_DFQ_VALID … #define B43legacy_MACCMD_CCA … #define B43legacy_MACCMD_BGNOISE … /* 802.11 core specific TM State Low flags */ #define B43legacy_TMSLOW_GMODE … #define B43legacy_TMSLOW_PLLREFSEL … #define B43legacy_TMSLOW_MACPHYCLKEN … #define B43legacy_TMSLOW_PHYRESET … #define B43legacy_TMSLOW_PHYCLKEN … /* 802.11 core specific TM State High flags */ #define B43legacy_TMSHIGH_FCLOCK … #define B43legacy_TMSHIGH_GPHY … #define B43legacy_UCODEFLAG_AUTODIV … /* Generic-Interrupt reasons. */ #define B43legacy_IRQ_MAC_SUSPENDED … #define B43legacy_IRQ_BEACON … #define B43legacy_IRQ_TBTT_INDI … #define B43legacy_IRQ_BEACON_TX_OK … #define B43legacy_IRQ_BEACON_CANCEL … #define B43legacy_IRQ_ATIM_END … #define B43legacy_IRQ_PMQ … #define B43legacy_IRQ_PIO_WORKAROUND … #define B43legacy_IRQ_MAC_TXERR … #define B43legacy_IRQ_PHY_TXERR … #define B43legacy_IRQ_PMEVENT … #define B43legacy_IRQ_TIMER0 … #define B43legacy_IRQ_TIMER1 … #define B43legacy_IRQ_DMA … #define B43legacy_IRQ_TXFIFO_FLUSH_OK … #define B43legacy_IRQ_CCA_MEASURE_OK … #define B43legacy_IRQ_NOISESAMPLE_OK … #define B43legacy_IRQ_UCODE_DEBUG … #define B43legacy_IRQ_RFKILL … #define B43legacy_IRQ_TX_OK … #define B43legacy_IRQ_PHY_G_CHANGED … #define B43legacy_IRQ_TIMEOUT … #define B43legacy_IRQ_ALL … #define B43legacy_IRQ_MASKTEMPLATE … /* Device specific rate values. * The actual values defined here are (rate_in_mbps * 2). * Some code depends on this. Don't change it. */ #define B43legacy_CCK_RATE_1MB … #define B43legacy_CCK_RATE_2MB … #define B43legacy_CCK_RATE_5MB … #define B43legacy_CCK_RATE_11MB … #define B43legacy_OFDM_RATE_6MB … #define B43legacy_OFDM_RATE_9MB … #define B43legacy_OFDM_RATE_12MB … #define B43legacy_OFDM_RATE_18MB … #define B43legacy_OFDM_RATE_24MB … #define B43legacy_OFDM_RATE_36MB … #define B43legacy_OFDM_RATE_48MB … #define B43legacy_OFDM_RATE_54MB … /* Convert a b43legacy rate value to a rate in 100kbps */ #define B43legacy_RATE_TO_100KBPS(rate) … #define B43legacy_DEFAULT_SHORT_RETRY_LIMIT … #define B43legacy_DEFAULT_LONG_RETRY_LIMIT … #define B43legacy_PHY_TX_BADNESS_LIMIT … /* Max size of a security key */ #define B43legacy_SEC_KEYSIZE … /* Security algorithms. */ enum { … }; /* Core Information Registers */ #define B43legacy_CIR_BASE … #define B43legacy_CIR_SBTPSFLAG … #define B43legacy_CIR_SBIMSTATE … #define B43legacy_CIR_SBINTVEC … #define B43legacy_CIR_SBTMSTATELOW … #define B43legacy_CIR_SBTMSTATEHIGH … #define B43legacy_CIR_SBIMCONFIGLOW … #define B43legacy_CIR_SB_ID_HI … /* sbtmstatehigh state flags */ #define B43legacy_SBTMSTATEHIGH_SERROR … #define B43legacy_SBTMSTATEHIGH_BUSY … #define B43legacy_SBTMSTATEHIGH_TIMEOUT … #define B43legacy_SBTMSTATEHIGH_G_PHY_AVAIL … #define B43legacy_SBTMSTATEHIGH_COREFLAGS … #define B43legacy_SBTMSTATEHIGH_DMA64BIT … #define B43legacy_SBTMSTATEHIGH_GATEDCLK … #define B43legacy_SBTMSTATEHIGH_BISTFAILED … #define B43legacy_SBTMSTATEHIGH_BISTCOMPLETE … /* sbimstate flags */ #define B43legacy_SBIMSTATE_IB_ERROR … #define B43legacy_SBIMSTATE_TIMEOUT … #define PFX … #ifdef assert # undef assert #endif #ifdef CONFIG_B43LEGACY_DEBUG #define B43legacy_WARN_ON(x) … #define B43legacy_BUG_ON(expr) … #define B43legacy_DEBUG … #else /* This will evaluate the argument even if debugging is disabled. */ static inline bool __b43legacy_warn_on_dummy(bool x) { return x; } #define B43legacy_WARN_ON … #define B43legacy_BUG_ON … #define B43legacy_DEBUG … #endif struct net_device; struct pci_dev; struct b43legacy_dmaring; struct b43legacy_pioqueue; /* The firmware file header */ #define B43legacy_FW_TYPE_UCODE … #define B43legacy_FW_TYPE_PCM … #define B43legacy_FW_TYPE_IV … struct b43legacy_fw_header { … } __packed; /* Initial Value file format */ #define B43legacy_IV_OFFSET_MASK … #define B43legacy_IV_32BIT … struct b43legacy_iv { … } __packed; #define B43legacy_PHYMODE(phytype) … #define B43legacy_PHYMODE_B … #define B43legacy_PHYMODE_G … /* Value pair to measure the LocalOscillator. */ struct b43legacy_lopair { … }; #define B43legacy_LO_COUNT … struct b43legacy_phy { … }; /* Data structures for DMA transmission, per 80211 core. */ struct b43legacy_dma { … }; /* Data structures for PIO transmission, per 80211 core. */ struct b43legacy_pio { … }; /* Context information for a noise calculation (Link Quality). */ struct b43legacy_noise_calculation { … }; struct b43legacy_stats { … }; struct b43legacy_key { … }; #define B43legacy_QOS_QUEUE_NUM … struct b43legacy_wldev; /* QOS parameters for a queue. */ struct b43legacy_qos_params { … }; /* Data structure for the WLAN parts (802.11 cores) of the b43legacy chip. */ struct b43legacy_wl { … }; /* Pointers to the firmware data and meta information about it. */ struct b43legacy_firmware { … }; /* Device (802.11 core) initialization status. */ enum { … }; #define b43legacy_status(wldev) … #define b43legacy_set_status(wldev, stat) … /* *** --- HOW LOCKING WORKS IN B43legacy --- *** * * You should always acquire both, wl->mutex and wl->irq_lock unless: * - You don't need to acquire wl->irq_lock, if the interface is stopped. * - You don't need to acquire wl->mutex in the IRQ handler, IRQ tasklet * and packet TX path (and _ONLY_ there.) */ /* Data structure for one wireless device (802.11 core) */ struct b43legacy_wldev { … }; static inline struct b43legacy_wl *hw_to_b43legacy_wl(struct ieee80211_hw *hw) { … } /* Helper function, which returns a boolean. * TRUE, if PIO is used; FALSE, if DMA is used. */ #if defined(CONFIG_B43LEGACY_DMA) && defined(CONFIG_B43LEGACY_PIO) static inline int b43legacy_using_pio(struct b43legacy_wldev *dev) { … } #elif defined(CONFIG_B43LEGACY_DMA) static inline int b43legacy_using_pio(struct b43legacy_wldev *dev) { return 0; } #elif defined(CONFIG_B43LEGACY_PIO) static inline int b43legacy_using_pio(struct b43legacy_wldev *dev) { return 1; } #else # error "Using neither DMA nor PIO? Confused..." #endif static inline struct b43legacy_wldev *dev_to_b43legacy_wldev(struct device *dev) { … } /* Is the device operating in a specified mode (IEEE80211_IF_TYPE_XXX). */ static inline int b43legacy_is_mode(struct b43legacy_wl *wl, int type) { … } static inline bool is_bcm_board_vendor(struct b43legacy_wldev *dev) { … } static inline u16 b43legacy_read16(struct b43legacy_wldev *dev, u16 offset) { … } static inline void b43legacy_write16(struct b43legacy_wldev *dev, u16 offset, u16 value) { … } static inline u32 b43legacy_read32(struct b43legacy_wldev *dev, u16 offset) { … } static inline void b43legacy_write32(struct b43legacy_wldev *dev, u16 offset, u32 value) { … } static inline struct b43legacy_lopair *b43legacy_get_lopair(struct b43legacy_phy *phy, u16 radio_attenuation, u16 baseband_attenuation) { … } /* Message printing */ __printf(2, 3) void b43legacyinfo(struct b43legacy_wl *wl, const char *fmt, ...); __printf(2, 3) void b43legacyerr(struct b43legacy_wl *wl, const char *fmt, ...); __printf(2, 3) void b43legacywarn(struct b43legacy_wl *wl, const char *fmt, ...); #if B43legacy_DEBUG __printf(2, 3) void b43legacydbg(struct b43legacy_wl *wl, const char *fmt, ...); #else /* DEBUG */ #define b43legacydbg … #endif /* DEBUG */ /* Macros for printing a value in Q5.2 format */ #define Q52_FMT … #define Q52_ARG(q52) … #endif /* B43legacy_H_ */
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