// SPDX-License-Identifier: ISC /* * Copyright (c) 2010 Broadcom Corporation */ #ifndef _SBCHIPC_H #define _SBCHIPC_H #include "defs.h" /* for PAD macro */ #define CHIPCREGOFFS(field) … struct chipcregs { … }; /* chipid */ #define CID_ID_MASK … #define CID_REV_MASK … #define CID_REV_SHIFT … #define CID_PKG_MASK … #define CID_PKG_SHIFT … #define CID_CC_MASK … #define CID_CC_SHIFT … #define CID_TYPE_MASK … #define CID_TYPE_SHIFT … /* capabilities */ #define CC_CAP_UARTS_MASK … #define CC_CAP_MIPSEB … #define CC_CAP_UCLKSEL … /* UARTs are driven by internal divided clock */ #define CC_CAP_UINTCLK … #define CC_CAP_UARTGPIO … #define CC_CAP_EXTBUS_MASK … #define CC_CAP_EXTBUS_NONE … #define CC_CAP_EXTBUS_FULL … #define CC_CAP_EXTBUS_PROG … #define CC_CAP_FLASH_MASK … #define CC_CAP_PLL_MASK … #define CC_CAP_PWR_CTL … #define CC_CAP_OTPSIZE … #define CC_CAP_OTPSIZE_SHIFT … #define CC_CAP_OTPSIZE_BASE … #define CC_CAP_JTAGP … #define CC_CAP_ROM … #define CC_CAP_BKPLN64 … #define CC_CAP_PMU … #define CC_CAP_SROM … /* Nand flash present, rev >= 35 */ #define CC_CAP_NFLASH … #define CC_CAP2_SECI … /* GSIO (spi/i2c) present, rev >= 37 */ #define CC_CAP2_GSIO … /* sr_control0, rev >= 48 */ #define CC_SR_CTL0_ENABLE_MASK … #define CC_SR_CTL0_ENABLE_SHIFT … #define CC_SR_CTL0_EN_SR_ENG_CLK_SHIFT … #define CC_SR_CTL0_RSRC_TRIGGER_SHIFT … #define CC_SR_CTL0_MIN_DIV_SHIFT … #define CC_SR_CTL0_EN_SBC_STBY_SHIFT … #define CC_SR_CTL0_EN_SR_ALP_CLK_MASK_SHIFT … #define CC_SR_CTL0_EN_SR_HT_CLK_SHIFT … #define CC_SR_CTL0_ALLOW_PIC_SHIFT … #define CC_SR_CTL0_MAX_SR_LQ_CLK_CNT_SHIFT … #define CC_SR_CTL0_EN_MEM_DISABLE_FOR_SLEEP … /* pmucapabilities */ #define PCAP_REV_MASK … #define PCAP_RC_MASK … #define PCAP_RC_SHIFT … #define PCAP_TC_MASK … #define PCAP_TC_SHIFT … #define PCAP_PC_MASK … #define PCAP_PC_SHIFT … #define PCAP_VC_MASK … #define PCAP_VC_SHIFT … #define PCAP_CC_MASK … #define PCAP_CC_SHIFT … #define PCAP5_PC_MASK … #define PCAP5_PC_SHIFT … #define PCAP5_VC_MASK … #define PCAP5_VC_SHIFT … #define PCAP5_CC_MASK … #define PCAP5_CC_SHIFT … /* pmucapabilites_ext PMU rev >= 15 */ #define PCAPEXT_SR_SUPPORTED_MASK … /* retention_ctl PMU rev >= 15 */ #define PMU_RCTL_MACPHY_DISABLE_MASK … #define PMU_RCTL_LOGIC_DISABLE_MASK … /* * Maximum delay for the PMU state transition in us. * This is an upper bound intended for spinwaits etc. */ #define PMU_MAX_TRANSITION_DLY … #endif /* _SBCHIPC_H */
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