/* SPDX-License-Identifier: GPL-2.0 */ #ifndef __MATROXFB_DAC1064_H__ #define __MATROXFB_DAC1064_H__ #include "matroxfb_base.h" #ifdef CONFIG_FB_MATROX_MYSTIQUE extern struct matrox_switch matrox_mystique; #endif #ifdef CONFIG_FB_MATROX_G extern struct matrox_switch matrox_G100; #endif #ifdef NEED_DAC1064 void DAC1064_global_init(struct matrox_fb_info *minfo); void DAC1064_global_restore(struct matrox_fb_info *minfo); #endif #define M1064_INDEX … #define M1064_PALWRADD … #define M1064_PALDATA … #define M1064_PIXRDMSK … #define M1064_PALRDADD … #define M1064_X_DATAREG … #define M1064_CURPOSXL … #define M1064_CURPOSXH … #define M1064_CURPOSYL … #define M1064_CURPOSYH … #define M1064_XCURADDL … #define M1064_XCURADDH … #define M1064_XCURCTRL … #define M1064_XCURCTRL_DIS … #define M1064_XCURCTRL_3COLOR … #define M1064_XCURCTRL_XGA … #define M1064_XCURCTRL_XWIN … /* drive DVI by standard(0)/DVI(1) PLL */ /* if set(1), C?DVICLKEN and C?DVICLKSEL must be set(1) */ #define M1064_XDVICLKCTRL_DVIDATAPATHSEL … /* drive CRTC1 by standard(0)/DVI(1) PLL */ #define M1064_XDVICLKCTRL_C1DVICLKSEL … /* drive CRTC2 by standard(0)/DVI(1) PLL */ #define M1064_XDVICLKCTRL_C2DVICLKSEL … /* pixel clock allowed to(0)/blocked from(1) driving CRTC1 */ #define M1064_XDVICLKCTRL_C1DVICLKEN … /* DVI PLL loop filter bandwidth selection bits */ #define M1064_XDVICLKCTRL_DVILOOPCTL … /* CRTC2 pixel clock allowed to(0)/blocked from(1) driving CRTC2 */ #define M1064_XDVICLKCTRL_C2DVICLKEN … /* P1PLL loop filter bandwidth selection */ #define M1064_XDVICLKCTRL_P1LOOPBWDTCTL … #define M1064_XCURCOL0RED … #define M1064_XCURCOL0GREEN … #define M1064_XCURCOL0BLUE … #define M1064_XCURCOL1RED … #define M1064_XCURCOL1GREEN … #define M1064_XCURCOL1BLUE … #define M1064_XDVICLKCTRL … #define M1064_XCURCOL2RED … #define M1064_XCURCOL2GREEN … #define M1064_XCURCOL2BLUE … #define DAC1064_XVREFCTRL … #define DAC1064_XVREFCTRL_INTERNAL … #define DAC1064_XVREFCTRL_EXTERNAL … #define DAC1064_XVREFCTRL_G100_DEFAULT … #define M1064_XMULCTRL … #define M1064_XMULCTRL_DEPTH_8BPP … #define M1064_XMULCTRL_DEPTH_15BPP_1BPP … #define M1064_XMULCTRL_DEPTH_16BPP … #define M1064_XMULCTRL_DEPTH_24BPP … #define M1064_XMULCTRL_DEPTH_24BPP_8BPP … #define M1064_XMULCTRL_2G8V16 … #define M1064_XMULCTRL_G16V16 … #define M1064_XMULCTRL_DEPTH_32BPP … #define M1064_XMULCTRL_GRAPHICS_PALETIZED … #define M1064_XMULCTRL_VIDEO_PALETIZED … #define M1064_XPIXCLKCTRL … #define M1064_XPIXCLKCTRL_SRC_PCI … #define M1064_XPIXCLKCTRL_SRC_PLL … #define M1064_XPIXCLKCTRL_SRC_EXT … #define M1064_XPIXCLKCTRL_SRC_SYS … #define M1064_XPIXCLKCTRL_SRC_PLL2 … #define M1064_XPIXCLKCTRL_SRC_MASK … #define M1064_XPIXCLKCTRL_EN … #define M1064_XPIXCLKCTRL_DIS … #define M1064_XPIXCLKCTRL_PLL_DOWN … #define M1064_XPIXCLKCTRL_PLL_UP … #define M1064_XGENCTRL … #define M1064_XGENCTRL_VS_0 … #define M1064_XGENCTRL_VS_1 … #define M1064_XGENCTRL_ALPHA_DIS … #define M1064_XGENCTRL_ALPHA_EN … #define M1064_XGENCTRL_BLACK_0IRE … #define M1064_XGENCTRL_BLACK_75IRE … #define M1064_XGENCTRL_SYNC_ON_GREEN … #define M1064_XGENCTRL_NO_SYNC_ON_GREEN … #define M1064_XGENCTRL_SYNC_ON_GREEN_MASK … #define M1064_XMISCCTRL … #define M1064_XMISCCTRL_DAC_DIS … #define M1064_XMISCCTRL_DAC_EN … #define M1064_XMISCCTRL_MFC_VGA … #define M1064_XMISCCTRL_MFC_MAFC … #define M1064_XMISCCTRL_MFC_DIS … #define GX00_XMISCCTRL_MFC_MAFC … #define GX00_XMISCCTRL_MFC_PANELLINK … #define GX00_XMISCCTRL_MFC_DIS … #define GX00_XMISCCTRL_MFC_MASK … #define M1064_XMISCCTRL_DAC_6BIT … #define M1064_XMISCCTRL_DAC_8BIT … #define M1064_XMISCCTRL_DAC_WIDTHMASK … #define M1064_XMISCCTRL_LUT_DIS … #define M1064_XMISCCTRL_LUT_EN … #define G400_XMISCCTRL_VDO_MAFC12 … #define G400_XMISCCTRL_VDO_BYPASS656 … #define G400_XMISCCTRL_VDO_C2_MAFC12 … #define G400_XMISCCTRL_VDO_C2_BYPASS656 … #define G400_XMISCCTRL_VDO_MASK … #define M1064_XGENIOCTRL … #define M1064_XGENIODATA … #define DAC1064_XSYSPLLM … #define DAC1064_XSYSPLLN … #define DAC1064_XSYSPLLP … #define DAC1064_XSYSPLLSTAT … #define M1064_XZOOMCTRL … #define M1064_XZOOMCTRL_1 … #define M1064_XZOOMCTRL_2 … #define M1064_XZOOMCTRL_4 … #define M1064_XSENSETEST … #define M1064_XSENSETEST_BCOMP … #define M1064_XSENSETEST_GCOMP … #define M1064_XSENSETEST_RCOMP … #define M1064_XSENSETEST_PDOWN … #define M1064_XSENSETEST_PUP … #define M1064_XCRCREML … #define M1064_XCRCREMH … #define M1064_XCRCBITSEL … #define M1064_XCOLKEYMASKL … #define M1064_XCOLKEYMASKH … #define M1064_XCOLKEYL … #define M1064_XCOLKEYH … #define M1064_XPIXPLLAM … #define M1064_XPIXPLLAN … #define M1064_XPIXPLLAP … #define M1064_XPIXPLLBM … #define M1064_XPIXPLLBN … #define M1064_XPIXPLLBP … #define M1064_XPIXPLLCM … #define M1064_XPIXPLLCN … #define M1064_XPIXPLLCP … #define M1064_XPIXPLLSTAT … #define M1064_XTVO_IDX … #define M1064_XTVO_DATA … #define M1064_XOUTPUTCONN … #define M1064_XSYNCCTRL … #define M1064_XVIDPLLSTAT … #define M1064_XVIDPLLP … #define M1064_XVIDPLLM … #define M1064_XVIDPLLN … #define M1064_XPWRCTRL … #define M1064_XPWRCTRL_PANELPDN … #define M1064_XPANMODE … enum POS1064 { … }; #endif /* __MATROXFB_DAC1064_H__ */
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