// SPDX-License-Identifier: ISC /* * Copyright (c) 2014 Broadcom Corporation */ #include <linux/kernel.h> #include <linux/delay.h> #include <linux/list.h> #include <linux/ssb/ssb_regs.h> #include <linux/bcma/bcma.h> #include <linux/bcma/bcma_regs.h> #include <defs.h> #include <soc.h> #include <brcm_hw_ids.h> #include <brcmu_utils.h> #include <chipcommon.h> #include "debug.h" #include "chip.h" /* SOC Interconnect types (aka chip types) */ #define SOCI_SB … #define SOCI_AI … /* PL-368 DMP definitions */ #define DMP_DESC_TYPE_MSK … #define DMP_DESC_EMPTY … #define DMP_DESC_VALID … #define DMP_DESC_COMPONENT … #define DMP_DESC_MASTER_PORT … #define DMP_DESC_ADDRESS … #define DMP_DESC_ADDRSIZE_GT32 … #define DMP_DESC_EOT … #define DMP_COMP_DESIGNER … #define DMP_COMP_DESIGNER_S … #define DMP_COMP_PARTNUM … #define DMP_COMP_PARTNUM_S … #define DMP_COMP_CLASS … #define DMP_COMP_CLASS_S … #define DMP_COMP_REVISION … #define DMP_COMP_REVISION_S … #define DMP_COMP_NUM_SWRAP … #define DMP_COMP_NUM_SWRAP_S … #define DMP_COMP_NUM_MWRAP … #define DMP_COMP_NUM_MWRAP_S … #define DMP_COMP_NUM_SPORT … #define DMP_COMP_NUM_SPORT_S … #define DMP_COMP_NUM_MPORT … #define DMP_COMP_NUM_MPORT_S … #define DMP_MASTER_PORT_UID … #define DMP_MASTER_PORT_UID_S … #define DMP_MASTER_PORT_NUM … #define DMP_MASTER_PORT_NUM_S … #define DMP_SLAVE_ADDR_BASE … #define DMP_SLAVE_ADDR_BASE_S … #define DMP_SLAVE_PORT_NUM … #define DMP_SLAVE_PORT_NUM_S … #define DMP_SLAVE_TYPE … #define DMP_SLAVE_TYPE_S … #define DMP_SLAVE_TYPE_SLAVE … #define DMP_SLAVE_TYPE_BRIDGE … #define DMP_SLAVE_TYPE_SWRAP … #define DMP_SLAVE_TYPE_MWRAP … #define DMP_SLAVE_SIZE_TYPE … #define DMP_SLAVE_SIZE_TYPE_S … #define DMP_SLAVE_SIZE_4K … #define DMP_SLAVE_SIZE_8K … #define DMP_SLAVE_SIZE_16K … #define DMP_SLAVE_SIZE_DESC … /* EROM CompIdentB */ #define CIB_REV_MASK … #define CIB_REV_SHIFT … /* ARM CR4 core specific control flag bits */ #define ARMCR4_BCMA_IOCTL_CPUHALT … /* D11 core specific control flag bits */ #define D11_BCMA_IOCTL_PHYCLOCKEN … #define D11_BCMA_IOCTL_PHYRESET … /* chip core base & ramsize */ /* bcm4329 */ /* SDIO device core, ID 0x829 */ #define BCM4329_CORE_BUS_BASE … /* internal memory core, ID 0x80e */ #define BCM4329_CORE_SOCRAM_BASE … /* ARM Cortex M3 core, ID 0x82a */ #define BCM4329_CORE_ARM_BASE … /* Max possibly supported memory size (limited by IO mapped memory) */ #define BRCMF_CHIP_MAX_MEMSIZE … #define CORE_SB(base, field) … #define SBCOREREV(sbidh) … struct sbconfig { … }; #define INVALID_RAMBASE … /* bankidx and bankinfo reg defines corerev >= 8 */ #define SOCRAM_BANKINFO_RETNTRAM_MASK … #define SOCRAM_BANKINFO_SZMASK … #define SOCRAM_BANKIDX_ROM_MASK … #define SOCRAM_BANKIDX_MEMTYPE_SHIFT … /* socram bankinfo memtype */ #define SOCRAM_MEMTYPE_RAM … #define SOCRAM_MEMTYPE_R0M … #define SOCRAM_MEMTYPE_DEVRAM … #define SOCRAM_BANKINFO_SZBASE … #define SRCI_LSS_MASK … #define SRCI_LSS_SHIFT … #define SRCI_SRNB_MASK … #define SRCI_SRNB_MASK_EXT … #define SRCI_SRNB_SHIFT … #define SRCI_SRBSZ_MASK … #define SRCI_SRBSZ_SHIFT … #define SR_BSZ_BASE … struct sbsocramregs { … }; #define SOCRAMREGOFFS(_f) … #define SYSMEMREGOFFS(_f) … #define ARMCR4_CAP … #define ARMCR4_BANKIDX … #define ARMCR4_BANKINFO … #define ARMCR4_BANKPDA … #define ARMCR4_TCBBNB_MASK … #define ARMCR4_TCBBNB_SHIFT … #define ARMCR4_TCBANB_MASK … #define ARMCR4_TCBANB_SHIFT … #define ARMCR4_BSZ_MASK … #define ARMCR4_BSZ_MULT … #define ARMCR4_BLK_1K_MASK … struct brcmf_core_priv { … }; struct brcmf_chip_priv { … }; static void brcmf_chip_sb_corerev(struct brcmf_chip_priv *ci, struct brcmf_core *core) { … } static bool brcmf_chip_sb_iscoreup(struct brcmf_core_priv *core) { … } static bool brcmf_chip_ai_iscoreup(struct brcmf_core_priv *core) { … } static void brcmf_chip_sb_coredisable(struct brcmf_core_priv *core, u32 prereset, u32 reset) { … } static void brcmf_chip_ai_coredisable(struct brcmf_core_priv *core, u32 prereset, u32 reset) { … } static void brcmf_chip_sb_resetcore(struct brcmf_core_priv *core, u32 prereset, u32 reset, u32 postreset) { … } static void brcmf_chip_ai_resetcore(struct brcmf_core_priv *core, u32 prereset, u32 reset, u32 postreset) { … } char *brcmf_chip_name(u32 id, u32 rev, char *buf, uint len) { … } static struct brcmf_core *brcmf_chip_add_core(struct brcmf_chip_priv *ci, u16 coreid, u32 base, u32 wrapbase) { … } /* safety check for chipinfo */ static int brcmf_chip_cores_check(struct brcmf_chip_priv *ci) { … } static u32 brcmf_chip_core_read32(struct brcmf_core_priv *core, u16 reg) { … } static void brcmf_chip_core_write32(struct brcmf_core_priv *core, u16 reg, u32 val) { … } static bool brcmf_chip_socram_banksize(struct brcmf_core_priv *core, u8 idx, u32 *banksize) { … } static void brcmf_chip_socram_ramsize(struct brcmf_core_priv *sr, u32 *ramsize, u32 *srsize) { … } /** Return the SYS MEM size */ static u32 brcmf_chip_sysmem_ramsize(struct brcmf_core_priv *sysmem) { … } /** Return the TCM-RAM size of the ARMCR4 core. */ static u32 brcmf_chip_tcm_ramsize(struct brcmf_core_priv *cr4) { … } static u32 brcmf_chip_tcm_rambase(struct brcmf_chip_priv *ci) { … } int brcmf_chip_get_raminfo(struct brcmf_chip *pub) { … } static u32 brcmf_chip_dmp_get_desc(struct brcmf_chip_priv *ci, u32 *eromaddr, u8 *type) { … } static int brcmf_chip_dmp_get_regaddr(struct brcmf_chip_priv *ci, u32 *eromaddr, u32 *regbase, u32 *wrapbase) { … } static int brcmf_chip_dmp_erom_scan(struct brcmf_chip_priv *ci) { … } u32 brcmf_chip_enum_base(u16 devid) { … } static int brcmf_chip_recognition(struct brcmf_chip_priv *ci) { … } static void brcmf_chip_disable_arm(struct brcmf_chip_priv *chip, u16 id) { … } static int brcmf_chip_setup(struct brcmf_chip_priv *chip) { … } struct brcmf_chip *brcmf_chip_attach(void *ctx, u16 devid, const struct brcmf_buscore_ops *ops) { … } void brcmf_chip_detach(struct brcmf_chip *pub) { … } struct brcmf_core *brcmf_chip_get_d11core(struct brcmf_chip *pub, u8 unit) { … } struct brcmf_core *brcmf_chip_get_core(struct brcmf_chip *pub, u16 coreid) { … } struct brcmf_core *brcmf_chip_get_chipcommon(struct brcmf_chip *pub) { … } struct brcmf_core *brcmf_chip_get_pmu(struct brcmf_chip *pub) { … } bool brcmf_chip_iscoreup(struct brcmf_core *pub) { … } void brcmf_chip_coredisable(struct brcmf_core *pub, u32 prereset, u32 reset) { … } void brcmf_chip_resetcore(struct brcmf_core *pub, u32 prereset, u32 reset, u32 postreset) { … } static void brcmf_chip_cm3_set_passive(struct brcmf_chip_priv *chip) { … } static bool brcmf_chip_cm3_set_active(struct brcmf_chip_priv *chip) { … } static inline void brcmf_chip_cr4_set_passive(struct brcmf_chip_priv *chip) { … } static bool brcmf_chip_cr4_set_active(struct brcmf_chip_priv *chip, u32 rstvec) { … } static inline void brcmf_chip_ca7_set_passive(struct brcmf_chip_priv *chip) { … } static bool brcmf_chip_ca7_set_active(struct brcmf_chip_priv *chip, u32 rstvec) { … } void brcmf_chip_set_passive(struct brcmf_chip *pub) { … } bool brcmf_chip_set_active(struct brcmf_chip *pub, u32 rstvec) { … } bool brcmf_chip_sr_capable(struct brcmf_chip *pub) { … }
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