/***************************************************************************\ |* *| |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *| |* *| |* NOTICE TO USER: The source code is copyrighted under U.S. and *| |* international laws. Users and possessors of this source code are *| |* hereby granted a nonexclusive, royalty-free copyright license to *| |* use this code in individual and commercial software. *| |* *| |* Any use of this source code must include, in the user documenta- *| |* tion and internal comments to the code, notices to the end user *| |* as follows: *| |* *| |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *| |* *| |* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *| |* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *| |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *| |* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *| |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *| |* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *| |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *| |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *| |* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *| |* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *| |* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *| |* *| |* U.S. Government End Users. This source code is a "commercial *| |* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *| |* consisting of "commercial computer software" and "commercial *| |* computer software documentation," as such terms are used in *| |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *| |* ment only as a commercial end item. Consistent with 48 C.F.R. *| |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *| |* all U.S. Government End Users acquire the source code with only *| |* those rights set forth herein. *| |* *| \***************************************************************************/ /* * GPL licensing note -- nVidia is allowing a liberal interpretation of * the documentation restriction above, to merely say that this nVidia's * copyright and disclaimer should be included with all code derived * from this source. -- Jeff Garzik <[email protected]>, 01/Nov/99 */ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/riva_hw.c,v 1.33 2002/08/05 20:47:06 mvojkovi Exp $ */ #include <linux/kernel.h> #include <linux/pci.h> #include <linux/pci_ids.h> #include "riva_hw.h" #include "riva_tbl.h" #include "nv_type.h" /* * This file is an OS-agnostic file used to make RIVA 128 and RIVA TNT * operate identically (except TNT has more memory and better 3D quality. */ static int nv3Busy ( RIVA_HW_INST *chip ) { … } static int nv4Busy ( RIVA_HW_INST *chip ) { … } static int nv10Busy ( RIVA_HW_INST *chip ) { … } static void vgaLockUnlock ( RIVA_HW_INST *chip, int Lock ) { … } static void nv3LockUnlock ( RIVA_HW_INST *chip, int Lock ) { … } static void nv4LockUnlock ( RIVA_HW_INST *chip, int Lock ) { … } static int ShowHideCursor ( RIVA_HW_INST *chip, int ShowHide ) { … } /****************************************************************************\ * * * The video arbitration routines calculate some "magic" numbers. Fixes * * the snow seen when accessing the framebuffer without it. * * It just works (I hope). * * * \****************************************************************************/ #define DEFAULT_GR_LWM … #define DEFAULT_VID_LWM … #define DEFAULT_GR_BURST_SIZE … #define DEFAULT_VID_BURST_SIZE … #define VIDEO … #define GRAPHICS … #define MPORT … #define ENGINE … #define GFIFO_SIZE … #define GFIFO_SIZE_128 … #define MFIFO_SIZE … #define VFIFO_SIZE … nv3_arb_info; nv3_fifo_info; nv3_sim_state; nv4_fifo_info; nv4_sim_state; nv10_fifo_info; nv10_sim_state; static int nv3_iterate(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_arb_info *ainfo) { … } static char nv3_arb(nv3_fifo_info * res_info, nv3_sim_state * state, nv3_arb_info *ainfo) { … } static char nv3_get_param(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_arb_info *ainfo) { … } static void nv3CalcArbitration ( nv3_fifo_info * res_info, nv3_sim_state * state ) { … } static void nv3UpdateArbitrationSettings ( unsigned VClk, unsigned pixelDepth, unsigned *burst, unsigned *lwm, RIVA_HW_INST *chip ) { … } static void nv4CalcArbitration ( nv4_fifo_info *fifo, nv4_sim_state *arb ) { … } static void nv4UpdateArbitrationSettings ( unsigned VClk, unsigned pixelDepth, unsigned *burst, unsigned *lwm, RIVA_HW_INST *chip ) { … } static void nv10CalcArbitration ( nv10_fifo_info *fifo, nv10_sim_state *arb ) { … } static void nv10UpdateArbitrationSettings ( unsigned VClk, unsigned pixelDepth, unsigned *burst, unsigned *lwm, RIVA_HW_INST *chip ) { … } static void nForceUpdateArbitrationSettings ( unsigned VClk, unsigned pixelDepth, unsigned *burst, unsigned *lwm, RIVA_HW_INST *chip, struct pci_dev *pdev ) { … } /****************************************************************************\ * * * RIVA Mode State Routines * * * \****************************************************************************/ /* * Calculate the Video Clock parameters for the PLL. */ static int CalcVClock ( int clockIn, int *clockOut, int *mOut, int *nOut, int *pOut, RIVA_HW_INST *chip ) { … } /* * Calculate extended mode parameters (SVGA) and save in a * mode state structure. */ int CalcStateExt ( RIVA_HW_INST *chip, RIVA_HW_STATE *state, struct pci_dev *pdev, int bpp, int width, int hDisplaySize, int height, int dotClock ) { … } /* * Load fixed function state and pre-calculated/stored state. */ #define LOAD_FIXED_STATE(tbl,dev) … #define LOAD_FIXED_STATE_8BPP(tbl,dev) … #define LOAD_FIXED_STATE_15BPP(tbl,dev) … #define LOAD_FIXED_STATE_16BPP(tbl,dev) … #define LOAD_FIXED_STATE_32BPP(tbl,dev) … static void UpdateFifoState ( RIVA_HW_INST *chip ) { … } static void LoadStateExt ( RIVA_HW_INST *chip, RIVA_HW_STATE *state ) { … } static void UnloadStateExt ( RIVA_HW_INST *chip, RIVA_HW_STATE *state ) { … } static void SetStartAddress ( RIVA_HW_INST *chip, unsigned start ) { … } static void SetStartAddress3 ( RIVA_HW_INST *chip, unsigned start ) { … } static void nv3SetSurfaces2D ( RIVA_HW_INST *chip, unsigned surf0, unsigned surf1 ) { … } static void nv4SetSurfaces2D ( RIVA_HW_INST *chip, unsigned surf0, unsigned surf1 ) { … } static void nv10SetSurfaces2D ( RIVA_HW_INST *chip, unsigned surf0, unsigned surf1 ) { … } static void nv3SetSurfaces3D ( RIVA_HW_INST *chip, unsigned surf0, unsigned surf1 ) { … } static void nv4SetSurfaces3D ( RIVA_HW_INST *chip, unsigned surf0, unsigned surf1 ) { … } static void nv10SetSurfaces3D ( RIVA_HW_INST *chip, unsigned surf0, unsigned surf1 ) { … } /****************************************************************************\ * * * Probe RIVA Chip Configuration * * * \****************************************************************************/ static void nv3GetConfig ( RIVA_HW_INST *chip ) { … } static void nv4GetConfig ( RIVA_HW_INST *chip ) { … } static void nv10GetConfig ( RIVA_HW_INST *chip, struct pci_dev *pdev, unsigned int chipset ) { … } int RivaGetConfig ( RIVA_HW_INST *chip, struct pci_dev *pdev, unsigned int chipset ) { … }
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